Coherent Composition of Signals by Means Progressive Focal Correction

Abstract

The invention relates to a beam former which performs coherent composition of signals originating from a given propagation direction, which are received by an array of N receiving transducers. The inventive methodology and devices are suitable for use in the following fields: radar, sonar, acoustic, seismology, ultrasound imaging (echography and non-destructive testing) and others. According to the invention, the beam former employs arrays having elements which can be distributed randomly. In particular, the invention can be used for dynamic focusing with deflection of the beam in azimuth and elevation, using two-dimensional arrays.

Description

BRIEF DESCRIPTION OF THE CONTENTS OF THE FIGURES

FIG. 1 shows the geometry used as an example with an array composed by N numbered elements 1, 2, 3, . . . k, . . . N-1 and N over axis x. The foci are located at ΔR intervals from a minimum distance R₀. The segment between a focus located in the polar coordinates (R,θ) and the k element of the array located in the Cartesian coordinates (x_k, 0) which length is L_k(R,θ) is shown.

FIG. 2 shows the general structure of a generic digital beamforming system in reception. It entails an array (10) with N elements (11) and a signal processing channel per each element. Each channel contains amplification circuits and signal conditioning AAS (12) and an A/D digitalizer (13). The outputs of the N digitalizers are processed by the beamformer CONF (14).

FIG. 3 shows the structure frequently used to execute the coherent composition of the signals according to known methods. It is composed by a gross delay system (22) and a fine delay system (23) which operation is managed from a local controller (24) that uses the contents of a dynamic focusing memory (25). The N delayed outputs f₁, f₂, . . . f_N are added in 20 to obtain the resulting rsequence.

FIG. 4 shows the structure of a digital processing channel, preferably used for the system that is the subject of this patent. It contains the amplifying and signal conditioning element AAS (12), the A/D digitalizer (13), a FIFO memory (43) that stores temporarily the acquired samples, a sampling clock generator (70) that is a fundamental element of the present invention and an enabling module of the dynamic focusing and control HFOC (80).

FIG. 5 shows the initial structure needed to effect the sampling clock generator (70) with the focal correction coded Q expressed with 1 bit in the MEM memory (75). The CNT counter (76) establishes the address to access this memory. The sampling clock CK_k of channel k is generated by logic distributed in the REG-A register (71a), the programmable length shift SHR-A (72), the FFA flip-flop (73), the multiplexer MUX (74) and the FFB flip-flop (77).

FIG. 6 shows the initial structure to do the sampling clock generator (70) with focal correction codes Q expressed with multiple bits in the MEM memory (75). The counter CNT (76) establishes the address to access this memory. The sampling clock CK_k of channel k is generated by logic distributed in the REG-A register (71a), the programmable length shift SHR-A (72), the programmable length shift SHR-B (78) and the set of inverters (75a).

FIG. 7 shows the initial structure to do the sampling clock generator (70) with focal correction codes Q expressed with one or more bits in the MEM memory (75). The counter CNT (76) establishes the address to access this memory. In this case a fixed or variable sample number can be inserted between foci, according to the contents of the register-counter RCM (71b) controlling the ng variable that establishes the length of the shift register (78). Variable ng, of 1 bit is provided by the CTRL control (90) shown in greater detail in the lower section of the figure. This unit is composed by a programmable counter module CMOD (91) which contents ant the value of the focal correction code Q form the address to one local memory MDM (92). Output g of this memory is inverted by (93) to obtain the ng signal. In this case the option to provide the focal offset code J from the same MEM memory of focal corrections code (75) does exist, as shown in a point line or, preferably, from the exterior and through a FIFO memory (79). As for the rest, the sampling clock CK_k of channel k is produced by the logic composed by the REG-A (71a) register, the length shift register SHR-A (72) and the length shift register SHR-B (78). The control unit CTRL provides, also, the cef output used to enable the counting of foci in the HFOC (80) unit shown in FIGS. 4 and 8.

FIG. 8 shows schematically the principle on which the HOFC unit (80) is based. This unit does the general control function of the acquisition. It is composed of a counter CNT-A (82) that is loaded by means of ida with the value N_A1, it is enabled with the cea signal and it is actuated with the low frequency clock cb. The terminal tca count acts on the S input of the FF flip-flop (83). Its aj output is delays an amount of master clock c cycles expressed by N_A2, by the shift register SHRG (84). The gate AND (81) produces a high level at the HFD output when its both inputs are on high. The flip-flop (83) is reset to 0 when its R input is raise when the signal tcf is activated.

The tcf signal is the terminal count of the CNT-F counter (86) that can be initialized with a specific number of NF foci when the idf signal is activated, its enabled with the cef signal and actuated with the low frequency cb clock. The CNT-S counter (88) counts the acquired samples, activating its FIN output when the N_s number programmed is reached. This programming is done by activating the ids signal, the counter is enabled with ces and is actuated with the low frequency cb clock.

FIG. 9 shows schematically the principle on which the APD unit (60) that does the apodization and dynamic aperture functions is based. It is composed of a multiplier (61) that obtains the product of input ek times the Ak coefficient and delivers the result hk to a multiplexer MUX (65). It also has a CNZ counter actuated by a cs clock and enabled by the HFD signal, which initial content is Mz, that is, the number of null samples to be provided by this channel to implement the dynamic aperture function. When the HFD signal is raised signal z is lifted to the output of the FF flip-flop (64), and the output ‘0’ delivered by unit (63) by the multiplexer MUX (65) that provides it as output f_k is selected. When the terminal count tc is reached, input R of the FF flip-flop (64) is activated and its output z is lowered to a low level prompting the multiplexer MUX (65) to select the h_k output of the multiplier MULT (61) and is delivered through output f_k.

FIG. 10 shows schematically the modular architecture of the system that is the object of this patent. A module (50) contains multiple sub-modules (40), each one with various elementary processors PE (30) which input are the signals received by the array (10) elements (11). The output of the elementary processors is added in (41) and the output of this adder device is used as one of the terms of the sum in a chain of adders (42) and FIFOs (52). The first sub-module substitutes this FIFO by a null input (51). The results provided by the adder (42) of the last sub-module are temporarily stored in a FIFO (56) to be, then added themselves in (58) to the results of a preceding module that have been stored in FIFO (57) in adder (58). Additionally the module contains a memory MJ (59) that provides the focal offset codes J to the different elementary processors PE (30).

FIG. 11 shows schematically, the principle on which the preferred embodiment of the adder (41) is based, with an example for 8 channels where multiple FIFOs (43) store temporarily the samples obtained at each elementary processor ek. The FIFOs (43) outputs are added by pairs in the adders (44), and the result stored in the FIFOs (47). Similarly, the outputs of said FIFOs are added in (48), and the final results are stored in FIFO (49) which output r represents the sum of the samples e₁ to e₈ delivered by the 8 elementary processors that are a sub-module in this example.

FIG. 12 shows a diagram of an example of a module (200) of the system that is the object of the present patent. It has two connectors (120a) and (120) b through which the analogic signals to be distributed by the buses (121a) and (121b) are entered to the double A/D converters (101). The samples provided by these converters are introduced by (106) in a FPGA (102) that does the digital processing functions corresponding to a sub-module (100), amongst which are the generation of the sampling clocks (105) and the provision of the results to the next sub-module via the bus (103). The last sub-module in the chain provides the results obtained to a FPGA (111) by the bus (104) to be combined with the preceding results of another module by bus (113), the subsequent results provided by buses (112) or (114). These buses are present in the connector (110). Also the FPGA (111) delivers control signals (115a) and (115b) to the amplifier and analogic conditioning circuits via connectors (130a) and (130b) respectively.

FIG. 13 shows the experimental measures done on the module described in FIG. (12), showing the absolute error in ns for each of the 32 channels.

EXAMPLE OF AN EMBODIMENT OF THE INVENTION

In all the cases described the sampling clock for each channel is obtained using very few hardware resources, essentially registers, counters and a memory used to store the focal correction codes, and the signal acquisition is achieved with a high temporal resolution.

Due to the high efficiency of the methodology described in what pertains to the use of hardware resources, and contrary to other embodiments, the PFC and the VPFC allow for the integration of multiple processing channels in one sole VLSI circuit, with other functions as described, even in devices of general use such as the FPGAs.

In a demonstration embodiment of this invention, a module contains 4 sub-modules, each of them with 8 elementary processors. This small system can operate with an active aperture of up to 32 elements in linear or sectorial scan with disperse aperture and arrays of 128 elements. A system that operates with dense or active apertures of up to 128 elements is configured with 4 modules. The system is scalable, adding 32 active elements for each new module installed.

FIG. 12 shows graphically the module's configuration done in a printed circuit card of 220×100 mm. the circuits corresponding to the analogic pre-processing of the signals with a possible excitation of the transducers, as well as the post-processing circuits, that in this particular embodiment are based on an integrated computer to which the Interface and Control Unit (ICU) is connected to the system described have been omitted.

Module (200) receives the analogic signals from 32 channels provided by the amplifier and conditioning circuits via the connectors (120a) and (120b). It contains four sub-modules (100) and one combiner done in the FPGA (111). The combiner receives signals processed by the bus (113) in a preceding module in the chain and sends the results to the following one by means of bus (114). The parameters are programmed from the ICU via the control bus (112), via which also the last module in the chain delivers the final results. Also, the FPGA (111) delivers a set of digital signals via the connectors (130a) and (130b) that are used by the analogic processing unit. This structure faithfully reflects the architecture shown in FIG. 10.

The analogic signals introduced by the connectors (120a) and (120b) are distributed to the sub-modules via buses (121a) and 121b respectively, where they are digitalized by the A/D converters (101). The digital outputs of the A/D converters are introduced in the FPGAs (10) via the buses (106). The sampling clock of said converters (105) is generated in the FPGAs (102) with the Progressive Focal Correction technique described in this specification.

The sub-modules are connected amongst themselves via the bidirectional buses (103). Together with bus (104), that connects the last sub-module to the combiner (111), these buses are used in one direction for the programming of parameters from the control one (112) and in the opposite direction to provide results to the sub-modules that are next in the chain or to the combiner (111 ).

The combiner does the coherent summation of the results obtained at the current module via the bus (104) to those results received from a preceding module by bus (113), providing the results of this process via bus (114) to the next module, or via bus (112) to the Interface and Control Unit. Either option is programmable.

In this embodiment the following components have been used: 16-10 bits each, type AD9218 double converters of Analog Devices have been used for the devices (101), 4 type XC2S200 FPGAs from Xilinx Inc. for devices (102) and one XC2S150 from Xilinx Inc., for device (111).

The system clock operates at 40 MHz, a speed at which the communication between sub-modules, modules and the ICU operate synchronically. Internally, part of the circuits also operate at this frequency or at a fraction that is determine by the sampling frequency, however, in the FPGAs (102), it is multiplied by 4 times the frequency of the system clock to obtain the 160 MHz master clock. The temporal resolution is then Tx=6.25 ns and the sampling error is theoretically delimited to |ε|≦3.125 ns. This allows the processing of analogic signals of up to 10 MHz with μ≧6 and up to 20 MHz with μ≧8, where μ is the relationship between the signal's period and the temporary resolution that affects the dynamic range and contrast of the images.

Each FPGA (102) contains the necessary circuits to implement all the digital processing of 8 channels, including:

• • Apodization, with 0≦A_k≦255/256 coefficients or disabled (A_k=1, ∀ k)
  • Dynamic aperture, where 0≦MZ_k≦2¹²
  • Beam deflection with a fixed focus, with 0≦NA_k≦2¹⁴
  • Dynamic focusing according to the Progressive Focal Correction theory as described above, with 1 bit 4096 focal correction codes per each channel
  • Programming the number of samples to be acquired, where 2≦Ns≦2¹⁷
  • Programming the number of samples between foci, where 4≦m≦64
  • Programming of the number of foci per acquisition, where 0≦NF≦2¹²
  • Programming of the output sampling frequency, where 2.5≦fs≦40 MHz
  • Circuits managed for energy efficiency and enabling of functions
  • Parameter programming and processing of results circuits
  • Circuits to verify the module, integrating a digital signal generator

The combiner contained in the FPGA (111) has circuits to do the following tasks:

• • Module management, transferring parameter values to the sub-modules via (104) and (103)
  • Compilation of results obtained from the preceding module via (113)
  • Composition of said results with those of the module, received via (104)
  • Provision of the combined results to the following module via (114)
  • Provision of the final results to the ICU via bus (112)
  • Circuits to compensate signal offset
  • Circuits to control the analogic pre-processing unit

FIG. (13) shows experimental measures relative to the absolute error in ns (in the ordinates) of the sampling instant in each of the 32 channels (in the abscissas) for a focus located at a 50 mm distance, with a 15° deflection angle, propagation speed of c=5900 ms⁻¹, and a 5 MHz linear array with elements uniformly distributed at intervals of d=0.8 mm.

The maximum theoretical error is of 3.125 ns, which is verified in 28 of the 32 channels. The greatest error in the 4 channels that exceeds the theoretical value is due to differences in the track layouts in the printed circuit and in the FPGAs of this experimental model, and is not a significant error at any rate. The average square error, which is more determining of the quality of the image, is of 1.9 ns.

Evidently, improvements may be introduced to the embodiment described herein, since there are devices that have a greater integration capacity. Also, other modifications that affect the type of A/D conversion, the distribution of devices, etc., can be introduced, since the model described is only submitted as a demonstrative example, without said modifications entailing a substantial change from the tenets of the methodology and system described in the present specification.

To apply the method, a case of sectorial ultrasonic image in pulse-echo with a linear transducer of N elements centered at origin and size D aperture can be considered. The aim is to cover a −45°≦θ≦45° sector with the image.

If f_R is the frequency of the received signal, in order to verify with sufficient margin the Nyquist criterion, a nominal sampling frequency of f_s=4 f_R is selected. Also, to maintain a high dynamic range and contrast in the image μ=fx/f_R=16 is selected, where f_x is the master clock frequency.

Considering the round trip travel path of the ultrasonic pulse, the interval between samples is:

ΔR=cT_S/2  (50)

Substituting the ΔR value given by Equation 1, when m=1 the result obtained is:

$\begin{array}{cc}v=\frac{T_s}{T_x}=4& \left(51\right)\end{array}$

When m samples are inserted between foci, the value of v=4 m. Applying now Equation 18, with |x_k|≦D/2, where D is the size of the aperture, the minimum distance to apply the Progressive Focal Correction technique with complete aperture is:

$\begin{array}{cc}\frac{R_0}{D}\ge \frac{1}{2}\frac{\mathrm{mv}-2a}{2\sqrt{\mathrm{amv}-a^2}}\cos \theta +\frac{1}{2}\mathrm{sen}\theta & \left(52\right)\end{array}$

Where a=2^b−1, where b is the number of bits with which to express the focal correction codes, provided that mv≧2a.

Table II shows the results of Equation (52) for b=1, 2 and 3 based on the (fixed) number of samples between foci.

It must be observed that the value R₀/D represents the minimum value of the number F# that can be used to implement the operation using the dynamic aperture function. Generally, a value of F#_min≦1 that is obtained with most of the combinations is accepted as valid.

TABLE II
F#min = R0/D to apply the PFCT with complete
aperture (−45° ≦ θ ≦ 45°)
	M	b = 1	b = 2	b = 3
	1	0.6	—	—
	2	0.8	0.4	—
	4	1	0.6	0.4
	8	1.4	0.9	0.6

Claims

1. A method for beam forming at reception called Progressive Focal Technique intended for applications in which a diversity of N transducers grouped in an array receive vibratory energy from foci Fi. i=0, 1, 2 . . . , located along a programmable direction, wherein it samples the signal received in each channel at the arrival instant from each focus with an absolute error lower than half a period of a master clock with a Tx period, in such a manner that the consecutive samples eki. i=0, 1, 2, . . . obtained in each channel k correspond to the consecutive values of the signal originated at each focus Fi, i=0, 1, 2, . . . , ensuring that each sample of the resulting signal ri, i=0, 1, 2, . . . is obtained by the sum of the N samples eki k=1, 2, . . . N:

2. A method of beam forming at reception according to claim 1 wherein the receptor channel that corresponds to the k element of the array, that includes circuits for the conditioning and amplifying of the signal, the sampling instant that corresponds to the first focus F0 is determined in non real time as based on the number of cycle NA(k) of the master clock that are between the origin of times selected with the constraint that all the times be positive and the arrival instant of the F0 focus to channel k, in such a manner that if the flight time of the signal that corresponds to the Fi focus to the k element is Ti (k), calculated as based in the geometry of the system and the speed of propagation of the waves in the medium, the NA(k) value is given by:

3. A method for beam forming at reception according to any of the previous claims wherein for other foci Fi i>0, the sampling instant at channel k is determined in real time based on the Qki value of b bits, stored in a focal correction memory associated to said channel k that codifies the advance to be applied to the nominal value v of master clock periods that is between two consecutive foci, where the Qki code is calculated in non real time based on the difference ΔTki between the arrival instant to the k element of the signals coming from the focus i-1 and the focus i as:

4. A method and system for beam forming at reception according to any of the previous claims wherein it allows inserting a fixed or programmable number m of samples between foci by means of a programmable counter module NM=m that is incremented every time that a new sample is acquired, and when it returns to zero the focal correction memory access address is incremented, making possible that a total of m samples share the same focal correction code Qki, which makes possible increasing the efficiency of the encoding process that may be a fraction of a bit per acquired sample while the sampling instant error is maintained basically bounded within half a period of the master clock since it has digital circuits that distribute uniformly the Qki advance amongst the samples m that are acquired between foci, circuits that are based on a table in which, before acquisition and for each possible value of Qki≦2b−1, a total of m bits g are programmed, and indicate for each of the m samples if the acquisition instant of said sample must be advanced (g=1) or not (g=0) by 1 master clock cycle, it being a particular case of the methodology exposed in the previous claims.

5. A method and system for beam forming at reception according to any of the previous claims wherein the distance between foci can be varied by means of the acquisition of a variable number of samples m between foci that is incremented from an initial value m0 when the value of a focal shift code Ji, of 1 bit associated to the Fi focus is Ji=1, an option called Variable Progressive Focal Correction technique, that increases the efficiency of the use of the focal correction memory by increasing the distance between foci with time, where the Ji value is common to all the channels for each value of i, that can be tabulated in a completely centralized manner for all the channels, in a partially centralized manner affecting a set of channels, as it is preferably done, or individually per channel, which allows establishing a balance between flexibility of application and memory efficiency; this can be implemented by simply substituting the register of the constant value m associated to each k channel by a counter that is loaded with the initial value m0 before initiating each acquisition and, during the acquisition time, said counter is incremented each time that signals are received from a new focus Fi and the Ji=1 code is received.

6. A method and system for beam forming at reception according to any of the previous claims wherein it has counters to determine the number of foci NF and of samples Ns to be acquired, considering that each focus may include the obtention of m samples, m being constant or variable so when the NF counter is overloaded the progressive focal correction mechanisms and the focal shift update mechanism are blocked, freezing also, the memory address that serves to access the focal correction codes in each channel, although the signal acquisition process may continue until the counter Ns that governs the number of samples to be acquired reaches the terminal value, facilitating that one sole memory per channel can store the focal correction codes for multiple angles of deflection, multiple configurations of the active aperture or a combination of both, the initial focal correction memory address can be programmed, at any rate, before each acquisition or be automatically obtained if the acquisition sequence corresponds to the order in which the focal correction codes have been stored for the current application.

7. A method and system for beam forming at reception according to any of the previous claims wherein it can operate optionally with a dynamic aperture, activating a counter associated to each channel k in which a number of output samples Nz(k) of null value is programmed from the beginning of the acquisition process to be combined with the corresponding samples of the remaining channels, and therefore for these Nz(k) samples the result is equivalent to eliminating the k element in the composition of the corresponding output samples, which effectively performs the dynamic aperture system.

8. A method and system for beam forming at reception according to any of the previous claims wherein it can insert an apodization function or multiplication of the values of each acquired sample times by constant that can be programmed for each channel.

9. A method and system for beam forming at reception according to any of the previous claims wherein it performs the coherent composition of the signal by means of a combination of distributed queues or FIFO memories and adders, preferably forming a tree structure in which each two FIFOs are associated to a 2 entry adder.

10. A method and system for beam forming at reception according to any of the previous claims wherein it facilitates its modular construction with a flexible architecture that allows for the coherent composition of an indefinite number of signals from the perspective of the logic, and for which certain number of channels are grouped to form a sub-module, several sub-modules configure a module and a system is configured by several modules, where all the channels are similar and process the acquired information in parallel.

11. A method and system for beam forming at reception according to any of the previous claims wherein it uses the methodology and constructive models described in this specification and shown in the attached figures below.