Patent Application
20120095948
The present disclosure relates to the field of computers, and specifically to the use of computers in event monitoring. Still more particularly, the present disclosure relates to the use of computers in utilizing cohorts to predict that a single entity will experience a particular future event.
A bit array is defined as an array structure that stores individual bits. Each individual bit can be associated with a particular characteristic or condition. For example, a particular bit in a bit array can be used to describe whether a particular entity described by the bit array has a particular disease, has purchased a particular product, has taken a particular medical test, etc. These values/characteristics/conditions can be accessed using a bit array index (also called a bitmap index), which associates a specific characteristic/condition to a specific bit location in the bit array.
A processor-implemented method, computer program product, and/or computer system predicts an occurrence of a future event. A first bit array, which describes characteristics of a single entity while experiencing a first event, is generated using values received from a set of physical test devices. After the first single entity experiences a different second event, a second bit array is generated from another set of physical test devices. The second bit array describes characteristics of an event cohort, which is made up of entities, other than the single entity, which also experience the second event, but which never experienced the first event. When another single entity experiences the first event, a determination is made as to whether that other single entity has characteristics from both the first bit array and the second bit array. If so, a prediction is made that the other single entity will also experience the second event.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
With reference now to the figures, and in particular to
Computer 102 includes a processor 104 that is coupled to a system bus 106. Processor 104 may utilize one or more processors, each of which has one or more processor cores. A video adapter 108, which drives/supports a display 110, is also coupled to system bus 106. System bus 106 is coupled via a bus bridge 112 to an input/output (I/O) bus 114. An I/O interface 116 is coupled to I/O bus 114. I/O interface 116 affords communication with various I/O devices, including a keyboard 118, a mouse 120, a media tray 122 (which may include storage devices such as CD-ROM drives, multi-media interfaces, etc.), a printer 124, and external USB port(s) 126. While the format of the ports connected to I/O interface 116 may be any known to those skilled in the art of computer architecture, in one embodiment some or all of these ports are universal serial bus (USB) ports.
As depicted, computer 102 is able to communicate with a software deploying server 150 using a network interface 130. Network 128 may be an external network such as the Internet, or an internal network such as an Ethernet or a virtual private network (VPN).
A hard drive interface 132 is also coupled to system bus 106. Hard drive interface 132 interfaces with a hard drive 134. In one embodiment, hard drive 134 populates a system memory 136, which is also coupled to system bus 106. System memory is defined as a lowest level of volatile memory in computer 102. This volatile memory includes additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers. Data that populates system memory 136 includes computer 102's operating system (OS) 138 and application programs 144.
OS 138 includes a shell 140, for providing transparent user access to resources such as application programs 144. Generally, shell 140 is a program that provides an interpreter and an interface between the user and the operating system. More specifically, shell 140 executes commands that are entered into a command line user interface or from a file. Thus, shell 140, also called a command processor, is generally the highest level of the operating system software hierarchy and serves as a command interpreter. The shell provides a system prompt, interprets commands entered by keyboard, mouse, or other user input media, and sends the interpreted command(s) to the appropriate lower levels of the operating system (e.g., a kernel 142) for processing. Note that while shell 140 is a text-based, line-oriented user interface, the present invention will equally well support other user interface modes, such as graphical, voice, gestural, etc.
As depicted, OS 138 also includes kernel 142, which includes lower levels of functionality for OS 138, including providing essential services required by other parts of OS 138 and application programs 144, including memory management, process and task management, disk management, and mouse and keyboard management.
Application programs 144 include a renderer, shown in exemplary manner as a browser 146. Browser 146 includes program modules and instructions enabling a world wide web (WWW) client (i.e., computer 102) to send and receive network messages to the Internet using hypertext transfer protocol (HTTP) messaging, thus enabling communication with software deploying server 150 and other computer systems.
Application programs 144 in computer 102's system memory (as well as software deploying server 150's system memory) also include a cohort-based event prediction program (CBEPP) 148. CBEPP 148 includes code for implementing the processes described below, including those described in
The hardware elements depicted in computer 102 are not intended to be exhaustive, but rather are representative to highlight essential components required by the present invention. For instance, computer 102 may include alternate memory storage devices such as magnetic cassettes, digital versatile disks (DVDs), Bernoulli cartridges, and the like. These and other variations are intended to be within the spirit and scope of the present invention.
Referring now to
With reference now to query block 206 in
As described in block 208, the processor then generates a second bit array. As depicted in the example shown in
Note that in one embodiment, the processor time shifts the second bit array before the second event to form a time-shifted second bit array. That is, rather than taking readings from the second set of physical test devices at the time of the second event (e.g., the heart attack), previously stored readings from the second set of physical test devices, which were taken before the heart attack, are retrieved (i.e., before some predetermined length of time before the second event). Thus, this time-shifted second bit array represents characteristics that are associated with the event cohort before the second event occurs.
In one embodiment, the processor time shifts the second bit array after the second event to form a time-shifted second bit array. That is, rather than taking readings from the second set of physical test devices at the time of the second event (e.g., the heart attack), the processor waits some predetermined length of time after the second event (e.g., the heart attack) and then retrieves readings from the second set of physical test devices. Thus, this time-shifted second bit array represents characteristics that are associated with the event cohort after the second event occurs. By time shifting the second bit array before and/or after the second event, new correlations between the second event and time-varied readings from the second set of physical test devices are made, thus leading to refined/revised hypotheses regarding the cause of the second event, particularly when viewed in the context of the first event's presence or absence.
In one embodiment, the processor identifies an event characteristic that is associated with a third event. The third event occurs contemporaneously with the second event. However, the third event has been predetermined to be unrelated to the second event. For example, assume that the second bit array for the event cohort includes bits that represent one of the characteristics of a person/entity experiencing the second event (e.g., a heart attack in the example presented herein). However, the processor may determine that these characteristics were actually caused by an unrelated event, such as having a chest cold. In order to “clean up” the second bit array, the processor removes any bit from the second bit array that describes the event characteristic that is associated with only the third event.
With reference now to block 210 in
The third bit array described in query block 212, and resulting in the activity described in block 214, includes values from both the first and second bit arrays. Thus, in the exemplary embodiment depicted in
In one embodiment, the level of matching provides a likelihood that the second event will occur. For example, a 90% match between the third bit array 320 with the first bit array 304 and the second bit array 314 makes the likelihood of the second single entity experiencing the second event more likely than if there were only an 80% match.
In one embodiment, the level of matching provides a time frame in which the second event will likely occur. For example, assume that the first single entity experienced the second event one year after he experienced the first event. A 100% match between the third bit array 320 with the first bit array 304 and the second bit array 314 makes it likely that the second single entity 318 will experience the second event within a year. Alternatively, a 90% match makes it likely that the second event will occur within two years, while an 80% match makes it likely that the second event will occur with five years. These likelihoods (both event and temporal) are based on the combined similarity between the second single entity 318 and the first single entity 302 and the event cohort 312. These likelihoods begin as hypotheses, which can later be confirmed with case studies.
Returning to
Note that in one embodiment, the processor has determined that the first event and the second event are different types of events (e.g., the first event is the receipt of pharmaceutical treatments and the second event is a heart attack). Nonetheless, in this embodiment the processor establishes a relationship between the first event and the second event through use of a Bayesian algorithm, which establishes a correlation between the first event and the second event based on common entities that experience the first event and the second event. This relationship is then used to bolster (reinforce) the hypothesis/prediction that the second single entity will experience the second event, as described above.
In an exemplary Bayesian analysis, assume that H represents the hypothesis that the second single entity will have a same increased chance of having a heart attack as the first single entity, and D represents that the second single entity has the same attributes (depicted in the first bit array) as the first single entity. This results in the Bayesian probability formula of:
where:
P(H|D) is the probability that a second single entity will have an increased likelihood of experiencing a heart attack (H) given that (I) the second single entity has the same attributes (both medical and non-medical) as the first single entity (D);
P(D|H) is the probability that, if the second single entity has an increased chance of having a heart attack, the second single entity will have the same attributes as the first single entity (i.e., even if the hypothesis P(H|D) is true, the two single entities may not have the exact same attributes);
P(H) is the probability that the second single entity will have an increased likelihood of having a heart attack regardless of any other information/facts; and
P(D) is the probability that the second single entity will have the same non-linear attributes as the first single entity regardless of any other information/facts.
For example, assume that past studies about entities similar to the first and second single entities show that any entity (patient) will have a higher heart attack rate relative to the group of unrelated patients 50% of the time (P(H)=50%). Assume further that the measured/deduced odds of two single entities having the same attributes (both medical and non-medical) are 6 out of 10 (P(D)=60%). Finally, assume that past studies have shown that two single entities having the same increased heart attack levels will have all of the same shared attributes 80% of the time (P(D|H)=80%). According to these values, the probability that the second single entity will have an increased likelihood of having a heart attack is therefore 66%:
However, if past studies have shown that two similar entities having the same increased likelihood of having a heart attack have all of the same shared attributes (i.e., the first bit array is the same for both the first and second entities) 100% of the time (P(D|H)=100%), then the probability that the second single entity will have an increased level of cancer is now 83%:
Note that in one embodiment, the first event may be a first medical diagnosis (e.g., diagnosing the patient as having cancer), while the second event may be a second medical diagnosis (e.g., diagnosing the patient as having heart disease). The same processes described herein are used to predict that a second single entity (as described above) will also be diagnosed with a heart disease, assuming that the bit array values described herein are in line with the process/examples presented above.
As described herein, one embodiment of the present invention refines the predictive power of the first bit array (when associated with a first event) with the correlation power of the second bit array (when associated with a second event). This refinement not only creates a more accurate prediction of whether the second event will occur, but also creates previously undeveloped hypotheses regarding the relationship and/or causation of the second event with respect to the first event.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of various embodiments of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Note further that any methods described in the present disclosure may be implemented through the use of a VHDL (VHSIC Hardware Description Language) program and a VHDL chip. VHDL is an exemplary design-entry language for Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), and other similar electronic devices. Thus, any software-implemented method described herein may be emulated by a hardware-based VHDL program, which is then applied to a VHDL chip, such as a FPGA.
Having thus described embodiments of the invention of the present application in detail and by reference to illustrative embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12907346 | Oct 2010 | US |
| Child | 13275483 | US |
