The present disclosure relates to a coil component.
In recent years, electronic devices have become increasingly wireless and power consumption in electronic circuits has increased. In particular, RF circuits are known to consume large amounts of power for transmitting, receiving, and processing RF communication signals. Therefore, a circuit that uses a divider circuit has been proposed to reduce power consumption (e.g., Japanese Unexamined Patent Application Publication No. 2017-534228).
When a coil component including a coil, such as a divider circuit, is realized with a multilayer electronic component, parasitic capacitance is generated between a coil, capacitor, or the like and an electrode, depending on the arrangement of the coil, capacitor, or the like formed inside the multilayer electronic component. It is possible that a coil component with generated parasitic capacitance cannot obtain required characteristics.
Therefore, preferred embodiments of the present invention provide coil components that each achieve required or desired characteristics.
A coil component according to a preferred embodiment of the present disclosure is a coil component including a plurality of coils in a multilayer body with a rectangular or substantially rectangular parallelepiped shape. The coil component includes an outer electrode located at least partially at a side surface of the multilayer body, a first coil conductor with a winding axis extending in a stacking direction of the multilayer body, and a second coil conductor with a winding axis extending in the stacking direction and located at a position where the second coil conductor does not overlap the first coil conductor when viewed in the stacking direction. The first coil conductor includes a plurality of conductor patterns stacked with an insulating layer interposed therebetween, and a connecting conductor to electrically connect the plurality of conductor patterns. When the multilayer body is divided by a bisecting line into a first region and a second region in a longitudinal direction of the multilayer body when viewed in the stacking direction, the first coil conductor is located in the first region. When viewed in the stacking direction, a straight line connecting the connecting conductor with the outer electrode at a minimum distance crosses an opening region of the first coil conductor.
According to a preferred embodiment the present disclosure, when viewed in the stacking direction, the straight line connecting the connecting conductor with the outer electrode at a minimum distance crosses the opening region of the first coil conductor. Thus, the first coil conductor and the outer electrode can be separated and the parasitic capacitance generated between the first coil conductor and the outer electrode can be reduced to obtain the characteristics required for the coil component.
The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.
The following is a description of coil components according to preferred embodiments of the present invention.
First, coil components according to preferred embodiments of the present invention will be described with reference to the drawings.
The coil component 1 is, for example, a divider circuit in which a first coil conductor that does not define a transformer and a second coil conductor that does define a transformer are arranged adjacent to each other. Although the following preferred embodiment is described using a divider circuit as the configuration of the coil component 1, a coil component including a plurality of coils in a multilayer body having a rectangular or substantially rectangular parallelepiped shape is not limited to a divider circuit, and a coil component with a similar configuration can be applied.
First, as illustrated in
The coil component 1 includes a multilayer body 3, in which a plurality of substrates with wiring for coils and capacitors are stacked as illustrated in
A first outer electrode 41, which defines the input terminal IN, a second outer electrode 42, which defines a GND terminal, a third outer electrode 43, which defines the output terminal OUT1, and a fourth outer electrode 44, which defines the output terminal OUT2, are provided at the four corners of the multilayer body 3. The first outer electrode 41 to the fourth outer electrode 44 need not be provided at the four corners of the multilayer body 3, but need only be provided at the outer periphery of the multilayer body 3. The number of outer electrodes provided at the outer periphery of the multilayer body 3 is not limited to four, but need only be plural.
The coil Lp1 is provided near the first outer electrode 41 and the fourth outer electrode 44, and has a winding axis extending in the stacking direction. The capacitor Cp1 is provided in the lower layer portion of the plurality of conductor patterns 10, and the coil Lp1 is provided in the upper layer portion. Via conductors 51 and 52 (connecting conductors) are provided to electrically connect the plurality of conductor patterns 10 that define the coil Lp1.
As illustrated in
Here, a coil component for comparison, which has a different arrangement of the via conductors 51 and 52, will be described.
In the coil component 1A, as illustrated in
Therefore, in the coil component 1 according to the present preferred embodiment, by providing the via conductors 51 and 52 at positions separated from the first outer electrode 41 and the fourth outer electrode 44, the parasitic capacitances Cs1 and Cs2 generated between the via conductors 51 and 52 and the first outer electrode 41 and the fourth outer electrode 44 are suppressed and the required isolation characteristics are obtained. Specifically, in the coil component 1, when the multilayer body 3 is divided by a bisecting line D into a first region A and a second region B in the longitudinal direction of the multilayer body 3 when viewed in the stacking direction, the coil Lp1 is located in the first region A, as illustrated in
The conductor of the coil Lp1 closer to the first outer electrode 41 and the fourth outer electrode 44 and the conductor of the coil Lp1 farther from the first outer electrode 41 and the fourth outer electrode 44 may be defined as follows. When the coil Lp1 is divided into two equal parts in the longitudinal direction (Y-direction) of the multilayer body 3 when viewed in the stacking direction, as illustrated in
The coil Lp1 is provided with two via conductors, namely, the via conductors 51 and 52, but is not limited to the case where all via conductors are provided in the second conductor 10B. It is sufficient that at least one of the via conductors 51 and 52 be provided in the second conductor. This allows at least one of the parasitic capacitances Cs1 and Cs2 to be suppressed.
Furthermore, since a magnetic flux flows inside a coil, the Q value of the coil deteriorates if a via conductor is provided inside the coil. However, among the coil Lp1 that does not define a transformer and the coils L1 to L3 that define a transformer included in the coil component 1, even if the Q value of the coil Lp1 that does not define a transformer deteriorates, it does not affect the bandpass characteristics of the LC resonator. Therefore, the via conductors 51 and 52 of the coil Lp1, for which the Q value need not be considered, can be provided inside the coil, thus allowing for a wider area for the coil to be placed within the multilayer body 3. This is particularly effective for the coil component 1 where the coil Lp1 and the coils L1 to L3 are arranged such that they do not overlap within the multilayer body 3.
Next, the configuration of each layer is described using exploded plan views.
First, each of the conductor patterns for coils and capacitors and the electrode patterns for outer electrodes are formed by screen printing of conductive paste (Ni paste) on ceramic green sheets 3a to 3l, which are substrates, as illustrated in
The ceramic green sheet 3a includes formed thereon electrode patterns 41a to 44a for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3b includes thereon electrode patterns 41b to 44b for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3c includes thereon electrode patterns 41c to 44c for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3d includes thereon electrode patterns 41d to 44d for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3e includes thereon electrode patterns 41e to 44e for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3f includes thereon electrode patterns 41f to 44f for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3g includes thereon electrode patterns 41g to 44g for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3h includes thereon electrode patterns 41h to 44h for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3i includes thereon electrode patterns 41i to 44i for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3j includes thereon electrode patterns 41j to 44j for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3k includes thereon electrode patterns 41k to 44k for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The ceramic green sheet 3l includes thereon electrode patterns 41l to 44l for the first outer electrode 41 to the fourth outer electrode 44, as illustrated in
The first outer electrode 41 is formed by electrically connecting the electrode patterns 41a to 41l on the ceramic green sheet 3a to the ceramic green sheet 3l. Similarly, the second outer electrode 42 is formed by electrically connecting the electrode patterns 42a to 42l on the ceramic green sheet 3a to the ceramic green sheet 3l. The third outer electrode 43 is formed by electrically connecting the electrode patterns 43a to 43l on the ceramic green sheet 3a to the ceramic green sheet 3l. The fourth outer electrode 44 is formed by electrically connecting the electrode patterns 44a to 44l on the ceramic green sheet 3a to the ceramic green sheet 3l.
In the coil component 1, at least one ceramic green sheet is stacked as each of the plurality of ceramic green sheets 3a to 3l illustrated in
As described above, the coil component 1 according to the present preferred embodiment includes a plurality of coils in a multilayer body 3 having a rectangular or substantially rectangular parallelepiped shape. The coil component 1 includes a first outer electrode 41 to a fourth outer electrode 44 provided at least partially at side surfaces of the multilayer body 3, a coil Lp1 with a winding axis extending in the stacking direction of the multilayer body 3, and coils L1 to L3 with a winding axis extending in the stacking direction and located at a position where the coils L1 to L3 do not overlap the coil Lp1 when viewed in the stacking direction. The coil Lp1 includes a plurality of conductor patterns 10d to 10i stacked with an insulating layer interposed therebetween and via conductors 51 and 52 to electrically connect the plurality of conductor patterns 10d to 10i. When the multilayer body 3 is divided by a bisecting line D into a first region A and a second region B in the longitudinal direction of the multilayer body 3 when viewed in the stacking direction, the coil Lp1 is located in the first region A. When viewed in the stacking direction, straight lines I1 and I2 connecting the via conductors 51 and 52 with the first outer electrode 41 and the fourth outer electrode 44 at a minimum distance cross the opening region O of the coil Lp1.
As a result, when the coil component 1 according to the present preferred embodiment is viewed in the stacking direction, the straight lines I1 and I2 connecting the via conductors 51 and 52 with the first outer electrode 41 and the fourth outer electrode 44 at a minimum distance cross the opening region O of the coil Lp1, thus separating the via conductors 51 and 52 from the first outer electrode 41 and the fourth outer electrode 44. The parasitic capacitance generated between the coil Lp1 and the first outer electrode 41 and the fourth outer electrode 44 can be suppressed, and the characteristics required for the coil component 1 (e.g., isolation characteristics between the output terminals OUT1 and OUT2) can be obtained.
It is preferred that the conductor closer to the first outer electrode 41 and the fourth outer electrodes 44 be the first conductor 10A, the conductor farther from the first outer electrode 41 and the fourth outer electrode 44 be the second conductor 10B, and at least one of the via conductors 51 and 52 be provided in the second conductor 10B. This allows the parasitic capacitance generated between the coil Lp1 and the first outer electrode 41 and the fourth outer electrode 44 to be suppressed and the characteristics required for the coil component 1 to be obtained.
At least one of the via conductors 51 and 52 is preferably provided at a side of the coil Lp1 parallel to the lateral direction of the multilayer body 3 when viewed in the stacking direction. This can suppress parasitic capacitance generated between the coil Lp1 and the first outer electrode 41 and the fourth outer electrode 44.
The via conductors 51 and 52 are preferably provided inside the coil Lp1. This allows for a wider area for the coil Lp1 and the coils L1 to L3 to be placed within the multilayer body 3.
When viewed in the stacking direction, the region S1 where the coil Lp1 is provided is preferably narrower than the region S2 where the coils L1 to L3 are provided. This allows for a wider area for the transformer unit to be placed within the multilayer body 3.
The coils L1 to L3 preferably define a transformer including a plurality of coils stacked in the stacking direction. This allows for a divider circuit in which the coil Lp1, which does not define a transformer, and the coils L1 to L3, which define a transformer, are arranged adjacent to each other.
The plurality of outer electrodes are preferably the first outer electrode 41 to the fourth outer electrode 44 located at the four corners of the multilayer body 3. This allows the plurality of outer electrodes at the four corners of the multilayer body 3 to be electrically connected to the outside.
In the coil component 1 described so far, the transformer unit has been described as including three coils L1 to L3 stacked in the stacking direction, but it may include two or more coils stacked in the stacking direction.
The coil component 1 described so far has been described as including a multilayer body 3 (ceramic body) including a plurality of stacked ceramic layers, but may have any dielectric multilayer structure.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
Number | Date | Country | Kind |
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2021-083940 | May 2021 | JP | national |
This application claims the benefit of priority to Japanese Patent Application No. 2021-083940 filed on May 18, 2021 and is a Continuation application of PCT Application No. PCT/JP2022/018739 filed on Apr. 25, 2022. The entire contents of each application are hereby incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/JP2022/018739 | Apr 2022 | US |
Child | 18382612 | US |