BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of a conventional CCFL circuit.
FIG. 2 is a graph showing uneven current flow in the lamps of FIG. 1.
FIG. 3 is a schematic block diagram of a CCFL circuit including a balance transformer current matching circuit.
FIG. 4 is a schematic block diagram of a CCFL circuit including a pulse skipping current matching control circuit according to an embodiment of the invention.
FIG. 5 is a graph showing lamp current waveforms with and without pulse skipping according to the embodiment.
FIG. 6 is a graph showing a pulse skipping waveform versus half-bridge voltage in the embodiment.
FIG. 7 is a schematic diagram of a CCFL circuit including a pulse skipping current matching control circuit according to another embodiment of the invention.
FIG. 8 is a schematic diagram of a function generator for generating control signals.
FIG. 9 is a timing diagram showing signals in the circuit of FIG. 8.