NSF Award
2331003
Society’s growing reliance on intelligent electronic systems risks significant disruption and loss from integrated circuit failure. Mitigating this threat requires building electronic systems that have been extensively tested to ensure that they are fully functional and defect-free. Modern integrated circuits contain billions of transistors that makes a complete exhaustive test of circuit functionality impractical and infeasible. Such tests are generated in practice, by considering the impact of likely manufacturing defects such as shorts and opens at various circuit locations, and developing a set of input test patterns whose correct binary output is altered by the existence of any targeted fault, identifying a bad integrated circuit. However, it is not practical to model and target all possible malfunctions in a large circuit, especially those that employ deeply scaled technologies, low supply voltages and high clock speeds. As a consequence, some faulty circuits inevitably escape post-manufacture testing because of incomplete test coverage and cause integrated circuit failure when deployed in operation. The goal of this research is to develop better and significantly more cost-effective test methods for state-of-the-art integrated circuits that can significantly impact the affordability and reliability of future computing systems that are increasingly pervasive in day-to-day societal applications and critical for national defense. The project will also help train new students in this strategic area, consistent with recent priorities for US leadership in semiconductor manufacturing. <br/><br/>Traditional test methods for integrated circuits generate test inputs that explicitly detect faulty behavior only at the terminals of the standard cell building blocks and the interconnections between these cells. It is now widely known that detection of defective devices can be enhanced by considering defects within the cell circuitry as well. To do this, currently, faults are injected one at a time at likely defect locations in the cell layout, followed by exhaustive circuit simulation of all possible input patterns to obtain cell level tests. The generated tests are then delivered to cells embedded in logic circuitry using circuit-level test generation algorithms. This has major drawbacks. First, it is expensive to characterize the full range of resistive defects at every possible location in large cells using exhaustive circuit simulation. In practice, only ideal shorts and opens are simulated, leading to test escapes. Second, this does not consider the significant impact of a timing delay in one cell on the delays of other interconnected cells. Third, existing test generation techniques such as cell aware test, can increase test size and application time by greater than fivefold. To address these issues, this project seeks to develop a new testing methodology that avoids exhaustive simulation, but instead uses analytical reasoning to generate tests for cell internal defects. Algorithms based on this analytic approach can generate compact tests that cover defects spanning large resistance ranges without the need for repeated simulations. Additionally, the delay impact of a single defect that affects multiple cells can also be effectively captured, minimizing the escape of timing faults.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
