NSF Award
2324946
All aspects of computing, spanning from small chips to large datacenters, bear a carbon footprint (CFP) price tag. Although the semiconductor industry has dedicated several decades to making chips smaller, faster, and more energy-efficient, the environmental impact has often been neglected. While technology scaling and electronic design automation (EDA) have facilitated designing energy-efficient very large-scale integrated (VLSI) systems that lower operational CFP, the overall environmental footprint has continued to grow, primarily due to carbon emissions from chip design and manufacturing processes. To ensure the sustainable use of modern computing, it is crucial to develop design techniques that not only meet power, performance, and area (PPA) targets but also consider the CFP. With today's trillion-transistor VLSI systems being designed by heterogeneously integrating a set of chiplets, each corresponding to a single die, onto a substrate to reduce costs, and new design methodologies to support these technologies being rolled out, now is an ideal time to help shape these methodologies to be more sustainable. The novelty of this project lies in paving a path toward sustainable design and manufacturing of VLSI systems through heterogeneous integration (HI). It defines metrics related to CFP and develops simulators and optimizers that integrate with design methodologies to measure and reduce the overall CFP. <br/><br/>Inspired by the principles of environmental sustainability—reduce, reuse, and recycle—this project aims to decrease the CFP associated with modern heterogeneous VLSI systems. HI systems offer great potential for sustainable computing by "reducing" carbon emissions through minimized computation required for designing each component from scratch and by "reusing" pre-designed chiplet intellectual property (IP) blocks through hierarchical approaches. Reusing chiplets across multiple designs, implemented in different technology nodes, within the current generation of integrated circuits (ICs) and even in future generations can significantly alleviate the manufacturing CFP. This project develops EDA approaches that (a) measure the carbon impact of heterogeneous VLSI system by building simulators that analyze its CFP across the design, manufacturing, and operational levels of a supply chain; (b) design methods for building high-performance HI systems, a new capability to be developed (since viable HI design flows do not exist today), tuned for efficient computation to reduce design-time carbon; (c) extend methodologies in the design task to incorporate the simulators from the measure task, to optimize the carbon footprint of a design, subject to PPA specifications on the HI design. This project outlines environmentally conscious computing practices by emphasizing the integration of CFP-related metrics into HI design methodologies and brings the community's attention to this critical issue in the semiconductor industry.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
