Collaborative Research: SHF: Medium: Differentiable Hardware Synthesis

Information

  • NSF Award
  • 2403134
Owner
  • Award Id
    2403134
  • Award Effective Date
    10/1/2024 - 4 months from now
  • Award Expiration Date
    9/30/2028 - 4 years from now
  • Award Amount
    $ 450,000.00
  • Award Instrument
    Standard Grant

Collaborative Research: SHF: Medium: Differentiable Hardware Synthesis

In the rapidly evolving digital world, creating high-performance and efficient computer hardware is crucial. Electronic design automation (EDA), a process that automates and optimizes the design of hardware, becomes even more critical and challenging with the ever-increasing complexity increases. This project introduces a novel approach to EDA, by solving circuit optimization problems with a blend of formal methods, machine learning, and parallel computing. This proposed research aims to transform the way computer chips are made, making the design process faster, less expensive, and more adaptable. The research findings and tools will be made publicly available to facilitate technology transfers and industry-academia interactions in a multidisciplinary community. The research findings and tools will be made publicly available to support technology transfers and interactions between industry and academia in a multidisciplinary community. This effort will also include active participation in educational and workforce development initiatives, involving high-school students and students from underrepresented groups.<br/><br/>In addressing the inherent limitations of existing synthesis solutions, such as unfavorable speed-quality trade-offs and inflexibility in leveraging domain knowledge, the presented research introduces a novel strategy that combines formal techniques with learning-based optimization. Specifically, the research takes a radically different approach by creating differentiable hardware synthesis techniques that are well-suited for heterogeneous computing. The key strategy involves the combination of formal techniques with learning-based optimization, which facilitates efficient global optimization, with or without the need for training data, while taking advantage of the computational power of parallel computing devices like graphics processing units (GPUs). This new approach distinguishes itself from conventional methods by its ability to scale global optimization through parallel computing resources, as well as its potential to combine other machine learning models to enable data-driven optimization via back-propagation. The developed algorithms and software will be made open-source and publicly accessible with comprehensive tutorials and educational materials.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

  • Program Officer
    Hu, X. Sharonxhu@nsf.gov7032928910
  • Min Amd Letter Date
    4/3/2024 - a month ago
  • Max Amd Letter Date
    4/3/2024 - a month ago
  • ARRA Amount

Institutions

  • Name
    University of Maryland, College Park
  • City
    COLLEGE PARK
  • State
    MD
  • Country
    United States
  • Address
    3112 LEE BUILDING
  • Postal Code
    207425100
  • Phone Number
    3014056269

Investigators

  • First Name
    Cunxi
  • Last Name
    Yu
  • Email Address
    cunxiyu@umd.edu
  • Start Date
    4/3/2024 12:00:00 AM

Program Element

  • Text
    Software & Hardware Foundation
  • Code
    779800

Program Reference

  • Text
    MEDIUM PROJECT
  • Code
    7924
  • Text
    DES AUTO FOR MICRO & NANO SYST
  • Code
    7945