NSF Award
2311544
The on-chip communication fabric connecting the cores, accelerators and the memory in chiplet-based architectures consumes a significant amount of power today and must be designed to not only provide adequate connectivity and performance, but also be very energy efficient and scalable, to satisfy future computing demands. Silicon photonics has the potential to alleviate some of the on-chip communication problems thanks to better performance-per-watt and higher bandwidth density. A key issue in addressing this design challenge today is the under-utilization of the expensive silicon photonics technology due to temporal and spatial fluctuation of traffic patterns. To make silicon photonics practical and viable, re-purposing the under-utilized resources for computation can speed up application execution and provide much-needed energy-efficient data transfers. The proposed research is timely and vital for the continued growth of chiplet-based heterogeneous manycore architectures. It is an organized effort that combines recent advances in technology, architecture, application, and machine learning into a promising integrated approach that will tackle one of the most critical challenges of computing systems of the future, namely the design of next-generation communication fabrics for high-performance, energy-efficient and scalable heterogeneous architectures with much-increased functionality and flexibility. All the research findings and simulation toolkits will be disseminated to the community via conference and journal publications, and a dedicated website. The research will also play a major role in education by integrating discovery with teaching and training. This research will continue to expand on outreach activities and broadening participation in computing by making the necessary efforts to attract and train underrepresented and minority students in this field. <br/><br/>This research will design a novel, dual-purpose photonic fabric that will not only enable power-efficient and scalable on-chip communications for heterogeneous multicores but will also function as a cost-efficient and high-performance neural network accelerator for diverse applications. The crux of the idea is to: (1) provide high-bandwidth and power-efficient data transfer between cores and accelerators during high network load, and (2) off-load key accelerator functions to the same network during low network load to maximize resource utilization and speedup computation, hence the dual-purpose nature of the photonic fabric. It is expected that the combined effects of meticulously orchestrating data communication (on-chip and off-chip), sharing hardware resources between communication and computation, and implementing optical neural computations will provide an extremely power-efficient and scalable platform for next-generation heterogeneous chiplet-based architectures. This research will result in (1) novel photonic architectures that can be leveraged for computing and communication simultaneously, (2) a fundamental understanding of photonic computation for implementing accelerator functions, (3) hardware techniques for photonic architectures to dynamically adapt to application demands to maximize the power-efficiency and improve resiliency, and (4) proof-of-concept and open-source tools that will expand and enhance the research capabilities of the computer architecture community in this critical area.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
