NSF Award
2403408
As monolithic chips reach their technological and practical limits, the integration of chiplets is emerging as the primary mechanism to continuously scale up processor performance, improve power efficiency, enhance IP reuse at low cost, and expedite time-to-market. This new concept of composable chiplets is particularly appealing to the artificial intelligence (AI) sector, which is in a pressing need to deliver computing chips to support increasingly complex and diverse cognitive algorithms. This project aims to pioneer such a computing system, including new architectural and design automation tools, for massive AI workloads. The envisioned system will benefit various scenarios, ranging from high-performance computing applications to mobile and edge devices. This project also addresses the skill shortage in the semiconductor area, a crucial aspect for reshoring the semiconductor industry. It involves training students in the areas of heterogeneous system design, AI architectures, and design automation. The investigators plan to improve the knowledge base through new curriculum development, engaging undergraduate students in research through Research Experiences for Undergraduates (REU) supplement, and participating in outreach programs customized for K-12 students. In addition, this project will advocate web-based knowledge dissemination including releasing software codes and novel designs. Several workshops and tutorials promoting chiplet-based co-design have been organized by the investigators and will be continued.<br/><br/>Distinguished from current practice of 2.5D/3D heterogeneous integration (HI), this project aims to transform the architecture of chiplet-based design through three unique perspectives: Miniaturization to reduce the chiplet size to the minimum (tiny chiplets) for high composability, guided by AI computing cores; Very-large-scale integration to integrate thousands of tiny chiplets to scale up computing power and diversity for big AI applications, offering unprecedented flexibility and efficiency for AI algorithm and system designers; and Reconfiguration on the package to enable adaptation to varying workloads and address thermal and reliability concerns in 2.5D/3D packaging. These innovations will push the limits of architecture and physical design, addressing challenges related to chiplet definition, interconnection, power and thermal integrity, and workload mapping. The objective is to create a suite of design automation tools, streamlining the complete design process of reconfigurable chiplet-based systems for big AI computing.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
