COLUMN-INTERLEAVED PIXEL ARRAY

Abstract

Shared-readout pixels conventionally disposed in two or more physical columns of a pixel array are spatially interleaved (merged) within a single physical column to yield a pixel array in which each physical pixel column includes two or more logical columns of shared-readout pixels coupled to respective logical-column output lines.

Description

TECHNICAL FIELD

The disclosure herein relates to integrated-circuit image sensors.

INTRODUCTION

Complementary metal oxide semiconductor (CMOS) image sensors are widely used in various imaging applications, such as consumer, industrial, and scientific imaging applications. Driven by the pursuit of higher spatial resolution and more compact sensor size, the pitch size of the pixels has been undergoing a rapid shrinking trend. Enabled by the advanced CMOS fabrication technologies, pixels with sub-micron pitch size (0.8 um and 0.7 um) have been used in consumer products.

Predominant constraints for further shrinking the CMOS pixel size include (i) the area required for transistors needed to read out the pixel signal, (ii) the minimum width, area, and spacing for the pixel implantation masks, and (iii) the minimum width and spacing for the metal wires that provide pixel control signals. While shared readout architectures are widely used to overcome the readout-transistor area and implantation-mask constraints (i.e., sharing a capacitive/floating-diffusion node, source-follower transistor and read-select transistor for multiple photodetection elements), those same architectures generally increase the requisite number transfer-gate control lines per pixel row (due to the separate transfer gate (TG) and TG control line needed for each photodetection element), driving up wire count and often forcing designers to compromise pixel performance to meet tight wire-spacing constraint.

DRAWINGS

The various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 illustrates an embodiment of image sensor having a column-interleaved pixel array, showing a conceptual progression from a non-interleaved architecture having a one-to-one correspondence between logical pixel columns to an interleaved architecture having multiple logical pixel columns per physical pixel column;

FIG. 2 illustrates considerations bearing on organization of a merged-column pixel array;

FIG. 3 illustrates another merged-column pixel-organization example, in this case assuming an 8-way shared-readout pixel having a non-unity aspect ratio;

FIG. 4 illustrates an embodiment of a fractional (or sub-pixel) column-interleaved array architecture; and

FIG. 5 illustrates an exemplary color filter array (CFA) that may be deployed over the illumination surface (integrated-circuit backside or frontside) of a column-interleaved pixel array according to the various embodiments presented herein.

DETAILED DESCRIPTION

In various embodiments herein, shared-readout pixels conventionally disposed in two or more physical columns of a pixel array are spatially interleaved (merged) within a single physical column to yield a pixel array in which each physical pixel column includes two or more logical columns of shared-readout pixels coupled to respective logical-column output lines. Because two or more neighboring shared-readout pixels within a given merged column drive different column outputs, those shared-readout pixels may be read-out simultaneously and thus controlled by a shared set of row control lines—increasing the spacing available for row-line routing by a factor of ‘N’, where N is the number of logical pixel columns per physical pixel column (or column output lines coupled to respective sets of shared-readout pixels within a given physical row) and referred to herein as a “merge ratio.”

In a number of column-interleaved pixel array embodiments presented herein (and host integrated-circuit image sensors in which those arrays are deployed), multiple shared-readout pixels are disposed in an interleaved structure to increase the horizontal space for the row control signal conductors. In general, the shared-readout pixels have n×m (‘n’ times ‘m’) photodetection elements or sub-pixels that may be independently read out (i.e., generation of output signal corresponding to charge accumulated within the sub-pixel photodetection element during an exposure interval) and reset via respective transfer gates, where m is the number of vertical pixels (extending along an axis parallel to the column output lines traversing the pixel array) and n is the number of horizontal pixels (extending along an axis orthogonal to the column output lines). As detailed below, two or more logical columns of shared-readout pixels (i.e., each logical column coupled to a respective column output line) may be integrally or fractionally interleaved within a physical column of the pixel array to yield expanded (row-to-row) control wire spacing. In an integrally interleaved pixel array, all photodetection elements (or sub-pixels) of a shared-readout pixel are collocated within a discrete area (i.e., no overlap with area/footprint of any other shared-readout pixel) so that two or more logical columns of shared-readout pixels are interleaved within a single physical column with granularity of whole shared-readout pixels. In a fractionally interleaved pixel array, by contrast, two or more logical columns of shared-readout pixels are interleaved with sub-pixel granularity (or granularity of sub-pixel groups or clusters) such that the footprint of each shared-readout pixel corresponding to a given logical column overlaps the footprint of at least one shared-readout pixel of another logical column. For example, two halves of the sub-pixels within a shared-readout pixel may be sufficiently offset from one another (in terms of physical layout) to allow placement (interleaving) of half of the sub-pixels within another shared-readout pixel (corresponding to a different logical pixel column) within the offset. These and other features and embodiments are described in further detail below.

FIG. 1 illustrates an embodiment of image sensor 100 having a column-interleaved pixel array, showing a conceptual progression from a non-interleaved architecture 104 having a one-to-one correspondence between logical pixel columns (i.e., each driving a respective column output line) and physical pixel columns to the interleaved architecture (100) having multiple logical pixel columns per physical pixel column. Referring first to non-interleaved architecture 104, a row control circuit 106 drives row control signals to each physical row of shared-readout pixels via respective sets of row control wires 107 to effect parallel readout (i.e., from all shared-readout pixels of a given row) via column-shared output lines 109 (i.e., column output lines extending to column readout circuitry 112), generally sequencing from row to row to effect a rolling shutter (i.e., each physical row readout in a respective “readout” time interval with the total number of readout intervals transpiring within an exposure interval). The row control wire count per physical row of shared-readout pixels is generally given by n+3, where ‘n’ is the number of photodetection elements per shared-readout pixel that are independently read-able via activation of respective transfer gates (i.e., n=number of transfer-gate (TG) control signals). The ‘+3’ term accounts for a reset line and row-select line (to switch on a reset transistor and row-select transistor, respectively, that constitute, along with a source-follower and capacitive/floating-diffusion node, a shared-readout circuit for driving a signal corresponding to photocharge transferred to the floating diffusion node from a given photodetection element or collection of photodetection elements) and boundary spacing needed between row control wires of neighboring rows. Thus, the area required for routing the row control wires increases linearly with ‘n’ and, as each wire (metal or other conductive trace) is generally constrained by fabrication rules (typically foundry specific) to have a minimum width ‘w’ and spacing ‘s’, the maximum number of wires per physical pixel array can be deterministically calculated with that maximum number constraining the shared-readout pixel pitch (i.e., distance d1 as shown in excerpt 120).

Following the conceptual progression shown at 130 the individual shared-readout pixels in adjacent pixel columns (i.e., driving respective column output lines) are offset by the shared-readout pixel pitch to make room for physically merging the pixels of the two original pixel columns excerpted in view 120 into a unified physical column (a 2:1 merge ratio in this example) as shown at 140. The row control lines coupled in common to each pair of pixels originally disposed in the same row (i.e., row control lines 107) remain electrically coupled as in architecture 104—e.g., via the stub connection shown at 131—so that each such pair of pixels remains in the same physical row (i.e., all coupled in common to the same set of row control lines) with that physical row effectively folded in two (according to the merge ratio, N) as shown at 150 within the finalized interleaved-column image sensor 100. Through this architectural change, the space available for row control line routing is expanded by a factor of N (the merge ratio) and, thus from d1 to d2 (2*d1 where ‘*’ denotes multiplication) in the two-column merge example shown. Note that, except for physical layout, the column readout circuitry 161 within column-interleaved architecture 100 may remain unchanged relative to the non-merged implementation at 112—ditto for the row control circuitry 163 (unchanged relative to non-merged implementation at 106) except for possible change in total number of physical rows.

FIG. 2 illustrates considerations bearing on organization of a merged-column pixel array. More specifically, given a merge ratio ‘N’ and assuming a given aspect ratio ‘pa’ for individual shared-readout pixels (i.e., pa=SR pixel width/height, where width is the shared-readout pixel dimension along an axis perpendicular to the column readout lines and height is the dimension along the column-readout axis) and that the image array as a whole has a desired aspect ratio ‘ar’, then the ratio of shared-readout pixels per physical row ‘nr’ (coupled in common to same row control lines) to the number of shared-readout pixels per logical column ‘nc’ (i.e., coupled in common to same column output line) may be calculated by nr/nc=ar*N²/pa (‘*’ denoting multiplication, ‘/’ denoting division, superscript denoting exponential). In the FIG. 2 example, for instance individual shared-readout (SR) pixels within array 180 have four sub-pixels (four photodetection elements or photodiode “storage wells” SW1-SW4 for photocharge accumulation (e⁻) together with four transfer gates TG1-TG4) clustered about a shared floating diffusion node (FD) with reset, source-follower and row-select transistors (RST, SF, RS) disposed adjacent the photodetection element—as shown in detail view 181—to yield a 1:1 shared-pixel aspect ratio (pa=1). A schematic implementation of the shared-readout pixel (referred to as a 2-horizontal by 2-vertical (2h×2v) “4-way shared-readout pixel in view of the four independently read-able sub-pixels arranged 2×2 along orthogonal axes) is shown at 183. Assuming, for purposes of example, a desired aspect ratio of 1:1 for the pixel array as a whole (ar=1) and merge ratio of 2:1 (N=2), then the number of shared-readout pixels per physical row will be four-times (4×) the number of shared-readout pixels per column output line. That is, nr=4nc as shown in conceptual array 180 so that, upon column merge, the structure shown at 190 is produced, with pixels in a given physical column alternately coupled to different column output lines (col outl, col out2 as shown in detail view 195).

FIG. 3 illustrates another merged-column pixel-organization example, in this case assuming an 8-way shared-readout pixel in a two-horizontal (2h) by four-vertical (4v) layout shown at 210 (with clusters of four sub-pixels disposed about respective floating diffusion regions (FD) that are intercoupled to one another (and thus electrically unified into a single capacitive node) and the gate of the source-follower transistor (SF) via metal layer connection 211) having a pixel aspect ratio of 1:2 (pa=0.5). Assuming the same merge ratio (N=2) and unity array aspect ratio (ar=1) as the FIG. 2 example, then nr=8nc as shown within conceptual array 215 to yield, upon column interleaving/merging, the unity aspect ratio column-interleaved array shown at 220.

FIG. 4 illustrates an embodiment of a fractional (or sub-pixel) column-interleaved array architecture, showing a progression from a non-interleaved architecture having 8-way shared readout pixels excerpted conceptually at 250—and more specifically from the detail view 251 of four neighboring SR pixels within the non-interleaved architecture 250—to a selected physical column of sub-pixel interleaved logical columns at 270. Referring to the four-SR-pixel detail view at 251, each of the SR pixels (shown at 261 in conceptual array 250) is organized in a 0.5 aspect (2h x 4v) such that respective clusters of four sub-pixels are disposed in upper (U) and lower (L) halves of the SR pixel footprint (area). The upper and lower sub-pixel clusters (groups of sub-pixels) in detail view 251 are subscripted to distinguish the non-interleaved physical row and column locations of their respective host SR pixels. As shown conceptually at 265, by (i) offsetting upper and lower clusters within each shared-readout pixel by a distance sufficient for insertion of an upper (or lower) sub-pixel cluster from another shared-readout pixel and (ii) offsetting shared-readout pixels coupled to the same column-output line by a distance sufficient for insertion of the counterpart lower (or upper) sub-pixel cluster from the other shared-readout pixel, the two shared-readout pixels may be column-interleaved at sub-pixel granularity (fractional column interleaving)—in this example, alternating halves of shared-readout pixels are column-interleaved as shown at 270, with all even numbered sub-pixel clusters (counting ordinally from top to bottom along the merged physical pixel column) read-able via a first column output line and all odd-numbered sub-pixel clusters read-able via a second column output line (with a readout circuit dedicated to/shared by each respective pair of even-numbered sub-pixel clusters and a separate readout circuit dedicated to/shared by each respective pair of odd-numbered sub-pixel clusters).

Sub-pixel-cluster-interleaved (fractional column-interleaved) layouts corresponding to the bottom pair of SR pixels within the conceptual views at 251, 265 and 270 are shown at 281, 285 and 290, respectively. That is, layouts of 8-way shared-pixels (282 and 283) are expanded and offset from one another as shown in the conceptual view at 285, and then merged (combined in a direction perpendicular to the column-readout-line axis) to yield the sub-pixel-cluster interleaved result shown at 290. Note that the placements of respective sets of shared-readout/shared-reset transistors (SF, RS, RST) corresponding to the two cluster-interleaved pixels (one set driving col outl, the other driving col out2) may be disposed in any practicable location within the footprint of the two cluster-interleaved shared-readout pixels and thus at locations other than those shown (e.g., SF, RS and RST transistors corresponding to col out2 could be located between sub-pixel clusters U₁₀ and L₁₁ instead of between L₁₁ and L₁₀).

FIG. 5 illustrates an exemplary color filter array (CFA) 300 that may be deployed over the illumination surface (integrated-circuit backside or frontside) of a column-interleaved pixel array according to the various embodiments herein, and more particularly with respect to the sub-pixel-cluster interleaved pixel array of FIG. 4. In the depicted embodiment, color filter elements 301 within the CFA are arranged in a Bayer pattern with each individual element overlaying (and thus filtering light for) a respective 4-sub-pixel cluster. Because the color filter elements within a physical column of a Bayer-pattered CFA alternate between two colors (green and blue as shown for col 303, or green and red as shown for col. 305), provision of a filter-element 301 per 4-sub-pixel cluster subjects all pixels in a given logical column (i.e., coupled to the same output line) to the same color filtering—that is, all are green filtered, all are blue filtered or all are red filtered. Thus, each column output line of the pixel array conveys signals corresponding exclusively to one color (green, red or blue), and the signals simultaneously read-out over the column output lines of the array (i.e., from a folded physical row as shown in outline 307) include the green-, red-, and blue-filtered signals corresponding to a complete Bayer pattern (two green signals, one red signal and one blue signal corresponding to photodetection elements or clusters thereof in a Bayer orientation). This effect is shown in layout view 320 with respect to two 4-sub-pixel interleaved SR pixels, driving “red” pixel readout signals via col outl and “green” pixel readout signals col out2, respectively—the two SR pixels being sub-pixel interleaved as shown at 290 of FIG. 4. Color filter arrays having color filter elements that pass light in wavelength-ranges other than those for green, red and blue may be disposed over the illumination surface of merged-column pixel arrays in other embodiments. For example, color filter arrays may be implemented with filter elements for white (deemed to be a “color” for purposes herein), yellow, magenta, cyan, emerald, or infrared light (or any other practicable range of electromagnetic radiation) instead of or in addition to red, blue and/or green color filter elements. Individual color elements may pass wavelengths in selected ranges (e.g., range of electromagnetic frequencies corresponding to “green” light) or block wavelengths in selected ranges to filter the light incident on a given photodetection element.

The various embodiments of column-interleaved pixel arrays, column readout logic, readout controllers, color filter arrays and so forth disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, computer storage media in various forms (e.g., optical, magnetic or semiconductor storage media, whether independently distributed in that manner, or stored “in situ” in an operating system).

When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image can thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology and symbols may imply details not required to practice those embodiments. For example, any of the specific shared-readout pixel counts, merge ratios, sub-pixel cluster sizes (i.e., number of sub-pixels per cluster), pixel aspect ratios, sub-pixel counts, pixel layouts, trace-routing arrangements, color filter array patterns and/or dispositions with respect to individual sub-pixels or clusters of sub-pixels, transistor types (e.g., NMOS or PMOS), component elements and the like can be different from those described above in alternative embodiments. Signal paths depicted or described as individual signal lines may instead be implemented by multi-conductor signal buses and vice-versa and may include multiple conductors per conveyed signal (e.g., differential or pseudo-differential signaling). The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening functional components or structures. Programming of any configurable parameters may be achieved, for example and without limitation, by loading a control value into a register or other storage circuit within an integrated circuit device in response to a host instruction (and thus controlling an operational aspect of the device and/or establishing a device configuration) or through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The terms “exemplary” and “embodiment” are used to express an example, not a preference or requirement. Also, the terms “may” and “can” are used interchangeably to denote optional (permissible) subject matter. The absence of either term should not be construed as meaning that a given feature or technique is required.

Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments can be applied in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1-21. (canceled)

22. An integrated-circuit image sensor comprising: first, second, third and fourth floating diffusion nodes disposed in order along a first axis within a pixel array such that the second floating diffusion node is closer to the first and third floating diffusion nodes than to the fourth floating diffusion node;a first electrical conductor coupled to the first and third floating diffusion nodes and not to the second or fourth floating diffusion nodes; anda second electrical conductor coupled to the second and fourth floating diffusion nodes and not to the first or third floating diffusion nodes.

23. The integrated-circuit image sensor of claim 22 wherein each of the first, second, third and fourth floating diffusion nodes is traversed by the first axis.

24. The integrated-circuit image sensor of claim 22 further comprising a first readout circuit coupled to the first and third floating diffusion nodes, and a second readout circuit coupled to the second and fourth floating diffusion nodes.

25. The integrated-circuit image sensor of claim 24 wherein the first readout circuit comprises a first transistor having a gate terminal coupled to the first and third floating diffusion nodes and a source terminal switchably coupled to a first output line, and the second readout circuit comprises a second transistor having a gate terminal coupled to the second and fourth floating diffusion nodes and a source terminal switchably coupled to a second output line.

26. The integrated-circuit image sensor of claim 25 wherein the first and second output lines each extend parallel to the first axis to a first periphery of the pixel array.

27. The integrated-circuit image sensor of claim 25 further comprising: first, second third and fourth photodetection elements disposed within the pixel array in order along the first axis; andfirst, second, third and fourth transfer gates coupled respectively between the first, second, third and fourth photodetection elements and the first, second, third and fourth floating diffusion nodes, respectively.

28. The integrated-circuit image sensor of claim 27 further comprising first and second transfer-gate control lines coupled respectively to the first and second transfer gates and that extend perpendicular to the first axis to a second periphery of the pixel array.

29. The integrated-circuit image sensor of claim 28 wherein the first and second transfer-gate control lines are also coupled to the third and fourth transfer gates, respectively.

30. The integrated-circuit image sensor of claim 29 wherein the first transfer-gate control line is coupled to at least one of the first and third transfer gates via a first conductive element that extends parallel to the first axis, and wherein the second transfer-gate control line is coupled to at least one of the second and fourth transfer gates via a second conductive element that extends parallel to the first axis.

31. The integrated-circuit device of claim 22 further comprising first, second, third and fourth pluralities of photodetection elements disposed about the first, second, third and fourth floating diffusion nodes, respectively.

32. An integrated-circuit image sensor comprising: first and second rows of pixels within a pixel array, each of the pixels having a respective photodetection element, readout circuit and transfer gate coupled between the photodetection element and readout circuit;a transfer-gate signal conductor extending across the pixel array parallel to the first and second rows of pixels and coupled to the respective transfer gates of the pixels within the first row; anda plurality of stub connections that extend from the transfer-gate signal conductor to respective transfer gates of the pixels within the second row.

33. The integrated-circuit image sensor of claim 32 wherein each of plurality of stub connections extends in a direction perpendicular to the transfer-gate signal conductor.

34. The integrated-circuit image sensor of claim 32 wherein transfer-gate signal conductor is routed over the first row of pixels.

35. The integrated-circuit image sensor of claim 32 wherein each of the first and second rows of pixels is constituted by a respective set of N pixels, and wherein plurality of stub connections comprises N stub connections.

36. The integrated-circuit image sensor of claim 35 wherein the first and second rows of pixels are disposed adjacent one another within the pixel array.

37. The integrated-circuit image sensor of claim 36 wherein each of the pixels within the first and second rows comprises the respective photodetection element together with at least one other photodetection element collectively disposed within a pixel area, and wherein the pixel area of each pixel within the first row overlaps the pixel area of a counterpart pixel within the second row.

38. The integrated-circuit image sensor of claim 32 further comprising a first plurality of output lines coupled to respective pixels of the first row and a second plurality of output lines coupled to respective pixels of the second row.

39. The integrated-circuit image sensor of claim 32 wherein each pixel within the first and second rows of pixels has, in addition to the respective photodetection element and transfer gate, (i) N−1 photodetection elements and (ii) N−1 transfer gates coupled between the additional N−1 photodetection elements and the readout circuit, and wherein the integrated-circuit image sensor further comprises: in addition to the transfer-gate signal conductor, N−1 additional transfer-gate signal conductors coupled to the pixels within one of the first and second rows of pixels; andin addition to the plurality of stub connections, a plurality of sets of stub connections each set of stub connections extending from a respective one of the N−1 additional transfer-gate signal conductors.

40. The integrated-circuit image sensor of claim 32 wherein the readout circuit within each of the pixels comprises a respective floating diffusion node and a respective transistor having a gate terminal coupled to the floating diffusion node.

41. An integrated-circuit image sensor comprising: first and second rows of pixels within a pixel array, each of the pixels having a respective photodetection element, readout circuit and transfer gate coupled between the photodetection element and readout circuit;a transfer-gate signal conductor that extends across the pixel array parallel to the first and second rows of pixels and coupled to the respective transfer gates of the pixels within the first row;a plurality of stub connections that extend from the transfer-gate signal conductor to respective transfer gates of the pixels within the second row; andmeans for asserting a control pulse on the transfer-gate signal conductor, the control pulse propagating via the transfer-gate signal conductor and the plurality of stub connections to the respective transfer gates within each of the pixels of the first and second rows.