Patent Application
20250123992
At least one embodiment generally pertains to integrated circuits (ICs), and more specifically, but not exclusively, to low activity, a combinational logic-based serializer.
In certain serializers integrated within communication systems, including high-speed serializer-deserializer (SERDES) systems, input data is retimed and multiplexed from a plurality of data inputs to a single, serial data output. The serialized data output may then be transmitted to an opposing link device, for example, or other devices. In these serializers, a clock signal is used to ensure proper generation and distribution of the data from the plurality of inputs to the single, serial data output. Further, in these serializers, the biggest contributor to overall serializer power is the power consumed by the last multiplexer stage (e.g., a high-rate M:1 multiplexer) and full-rate clock distribution.
Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:
As described above, the biggest contributor to overall serializer power is the power consumed by the last multiplexer stage (e.g., a high-rate M:1 multiplexer) and full-rate clock distribution. Aspects and embodiments of the present disclosure address the above deficiencies by replacing one or more clocked multiplexer stages with combinational logic operations that obviate the need for full-rate clocking of at least one multiplexer stage. In some embodiments, the replacement includes replacing a final multiplexer stage with combinational logic.
In various embodiments, using such combinational logic, clocked multiplexer stages are completely or partially omitted by precoding the parallelized data received. For example, if logic circuitry of an exclusive or (XOR) is employed within a final multiplexer stage without a clock signal, a precoder circuit may be employed before the logic circuitry in the serialization chain of components to format the parallelized data in a way that the XOR functionality can generate the serialized data output from the precoded data.
In at least one embodiment, a serializer (e.g., an integrated circuit) includes logic circuitry configured to output serialized data from multiple precoded data inputs without using a clock signal. In some embodiments, the serializer also includes a precoder circuit, responsive to the clock signal, that generates multiple precoded data inputs based on the timing of data symbols positioned within multiple data inputs to the serializer. The precoder circuit, for example, may cause timing of transitional changes in the data symbols within the multiple data inputs to also appear in the multiple precoded data inputs that exit the precoder circuit. These transitional changes, however, may be formatted in the multiple precoded data inputs in a way that enables the logic circuitry to, without the clock signal, generate the serialized data that would have been expected from operations of a clock-driven M:1 multiplexer. Here, M can be the number of the multiple data inputs to the serializer or the precoder circuit.
In some embodiments, the serializer also includes a retimer circuit to generate multiple retimed data inputs based on a clock signal. In these embodiments, the precoder circuit generates, from the multiple retimer data inputs, multiple precoded data inputs based on timing of data symbols positioned within the multiple retimer data inputs. The serializer also includes logic circuitry configured to output serialized data from the multiple precoded data inputs without using the clock signal.
Therefore, advantages of the IC chips, dice, systems, and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, a significant reduction in power consumption by a serializer method, device, or system. The decrease in power consumption, and concomitant cost savings, may be achieved without a loss of speed or accuracy of serialized data outputs. Other advantages will be apparent to those skilled in the art of serializers and SERDES devices, as will be discussed hereinafter.
In at least some embodiments, the combinational serializer 103 includes a serializer 102, a second set of input lines 104 that are fewer in number than the first set of input lines 101, and a multiplexer circuit 106 coupled to the serializer 102 via the second set of input lines 104. In some embodiments, the serializer 102 is an M:N serializer that is timed off a clock signal (clk). In these embodiments, M is the number of the first set of input lines 101, and N is the number of the second set of input lines 104. Thus, in some embodiments, the serializer 102 serializes input data (e.g., parallel data) from the first set of input lines 101 to the second set of input lines 104. In some embodiments, the multiplexer 106 is an N:1 multiplexer where N is the number of the second set of input lines 104, and the multiplexer 106 is clocked, e.g., by the same clock signal (clk) as the serializer 102.
Further, in various embodiments, the multiplexer 106 is replaced with logic circuitry 130 configured to output serialized data from multiple precoded data inputs without use of the clock signal. In these embodiments, the serializer 102 receives the clock signal (clk) and includes a precoder circuit 120 configured to, responsive to the clock signal, generate the multiple precoded data inputs based on timing of data symbols positioned within multiple data inputs. For example, in some embodiments, the precoder circuit 120 causes timing of transitional changes in the data symbols within multiple data inputs (e.g., from the first set of input lines 101) to also appear in the multiple precoded data inputs in a way that enables the logic circuitry 130 to generate the serialized data that would have been expected from operations of the N:1 multiplexer, where N is the number of data inputs, e.g., from the second set of input lines 104.
In various embodiments, the logic circuitry 230 is an exclusive OR (XOR) gate with a number of inputs matching a number of the multiple precoded data inputs 222. In other embodiments, the logic circuitry 230 is a not-exclusive OR (XNOR) gate with a number of inputs matching a number of the multiple precoded data inputs 222. Other logic circuitry capable of changing an output for a change in each single precoded input is also envisioned. In various embodiments, the precoder circuit 220 includes including XOR, XNOR, and/or other summing logic implemented with a modulo 2 function to the inputs or outputs. Thus, as is illustrated according to these embodiments, the precoder circuit 220 and the logic circuitry 230 may replace all multiplexer stages, e.g., the M:N serializer 102 and the multiplexer 106 of the data serializer system 100 of
In various embodiments, the precoding designed into the precoder circuit 220 depends on both the logic circuitry 230 (e.g., logic function implemented by the logic circuitry 230) as well as whether the precoding is preceded or followed by a multiplexer stage within the serialization chain. As such, many possible precoding functions are possible and envisioned. In one embodiment, a precoding function implemented by the precoder 220 is illustrated in Equation (1), e.g., and can be represent the logic function (e.g., module 2 summuation) implemented by the logic circuitry 230 as an XOR combination of the inputs.
An example of the resultant logic following Equation (1) for a 2:1 XOR combination is illustrated in Equation (2) and Equation (3).
Further, the logic of Equations (2)-(3) may be implemented by the precoder circuit 220, as illustrated in an example precoder circuit 320 of
In at least some embodiments, the retimer circuit 410 generates multiple retimed data inputs based on a clock signal (clk), where the outputs of the retimer circuit 410 have been shifted in time. In these embodiments, the precoder circuit 420 generates, from the multiple retimer data inputs, multiple precoded data inputs 422 based on timing of data symbols positioned within the multiple retimer data inputs. As is illustrated, for example, in0·z−1 is replaced with a0·z−1, in1·z−1 is replaced with a1·z−1, and so forth. In these embodiments, the logic circuitry 430 implements 4:1 serialization and is configured to output serialized data from the multiple precoded data inputs without use of the clock signal.
An example of the resultant logic following Equation (1) for a 4:1 XOR combination is illustrated in Equations (4)-(7), illustrating the multiple precoded data inputs 422, namely a0, a1, a2, and a3.
The logic of Equations (4)-(7) may be implemented by the precoder circuit 220, as illustrated in an example precoder circuit 520 of
In some embodiments, the pair of 2:1 multiplexers 625 serializes the multiple precoded inputs (b0-b3) to N parallel lines (a0 and a1). In this way, serialized, multiple precoded inputs (b0-b3) can be processed through the logic circuitry 630. In some embodiments, the use of the pair of 2:1 multiplexers 625 enables the precoder circuit 620 to operate at a lowest available data rate (or at least a reduced data rate compared to a data rate of the serialized data output by the logic circuitry 630), followed by operating the pair of 2:1 multiplexers 625 at an intermediate data rate, and the logic function 630 replacing a multiplexer that would normally operate at a full data rate. In the illustrated embodiment, the logic circuitry 630 is an XOR function.
In an illustrated embodiment of
More specifically, in some embodiments, the four XOR gates include a first XOR gate 705, a second XOR gate 715, a third XOR gate 725, and a fourth XOR gate 735, which respectively generate the multiple precoded data inputs (b0-b3). In these embodiments, the inputs to the first XOR gate 705 include the first retimed data input (inRet0) and a delayed (e.g., z−1) fourth output (b3) of the fourth XOR gate 735. In some embodiments, the inputs to the second XOR gate 715 include the second retimed data input (inRet1) and the output (b0) of the first XOR gate 705. In embodiments, the inputs to the third XOR gate 725 include the third retimed data input (inRet2) and the output (b1) of the second XOR gate 715. Finally, in embodiments, the inputs to the fourth XOR gate 735 include the fourth retimed data input (inRet3) and the output (b2) of the third XOR gate 725. In other embodiments, when the logic circuitry 630 is an XNOR gate, the precoder circuit 620 is implemented using four XNOR gates, each that receives an adjacent output as an input in addition to one of the multiple retimer data inputs (inRet0 to inRet3).
In some embodiments, the pair of 4:1 multiplexers 825 serializes the multiple precoded inputs (b0-b7) to N parallel lines (a0 and a1). In this way, serialized, multiple precoded inputs (b0-b7) can be processed through the logic circuitry 830. In some embodiments, the use of the pair of 4:1 multiplexers 825 enables the precoder circuit 820 to operate at a lowest available data rate (or at least a reduced data rate compared to a data rate of the serialized data output by the logic circuitry 830), followed by operating the pair of 4:1 multiplexers 825 at an intermediate data rate and the logic function 830 replacing a multiplexer that would normally operate at a full data rate. In the illustrated embodiment, the logic circuitry 830 is an XOR function.
In an illustrated embodiment of
More specifically, in some embodiments, the eight XOR gates include a first XOR gate 905, a second XOR gate 915, a third XOR gate 925, a fourth XOR gate 935, a fifth XOR gate 945, a sixth XOR gate 955, a seventh XOR gate 965, and an eighth XOR gate 975, which respectively generate the multiple precoded data inputs (b0-b7). In these embodiments, the inputs to the first XOR gate 905 include the first retimed data input (inRet0) and a delayed (e.g., z−1) eighth output (b7) of the eighth XOR gate 975. In embodiments, the inputs to the second XOR gate 915 include the second retimed data input (inRet1) and the output (b0) of the first XOR gate 905. In embodiments, the inputs to the third XOR gate 925 include the third retimed data input (inRet2) and the output (b1) of the second XOR gate 915. In embodiments, the inputs to the fourth XOR gate 935 include the fourth retimed data input (inRet3) and the output (b2) of the third XOR gate 925. In embodiments, the inputs to the fifth XOR gate 945 include the fifth retimed data input (inRet4) and the output (b3) of the fourth XOR gate 935. In embodiments, the inputs to the sixth XOR gate 955 include the sixth retimed data input (inRet5) and the output (b4) of the fourth XOR gate 945. In embodiments, the inputs to the seventh XOR gate 965 include the seventh retimed data input (inRet6) and the output (b5) of the fifth XOR gate 955. In embodiments, the inputs to the eighth XOR gate 975 include the eighth retimed data input (inRet7) and the output (b6) of the seventh XOR gate 965. In other embodiments, when the logic circuitry 830 is an XNOR gate, the precoder circuit 820 is implemented using eight XNOR gates, each that receives an adjacent output as an input in addition to one of the multiple retimer data inputs (inRet0 to inRet7).
At operation 1010, the processing logic employs a logic function to output serialized data from multiple precoded data inputs without use of an integrated circuit clock received by the combinational serializer.
At operation 1020, the processing logic employs a precoding function consistent with the logic function to, responsive to the integrated circuit clock, generate multiple precoded data inputs based on timing of data symbols positioned within multiple data inputs.
In some embodiments of the method 1000, the precoding function causes timing of transitional changes in the data symbols within the multiple data inputs to also appear in the multiple precoded data inputs in a way that enables the logic function to generate the serialized data that would have been generated by a clock-driven multiplexer.
Other variations are within the scope of the present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to a specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in appended claims.
Use of terms “a” and “an” and “the” and similar referents in the context of describing disclosed embodiments (especially in the context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. “Connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitations of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, the use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but subset and corresponding set may be equal.
Conjunctive language, such as phrases of the form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with the context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of the set of A and B and C. For instance, in an illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, the term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). In at least one embodiment, the number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, the phrase “based on” means “based at least in part on” and not “based solely on.”
Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause a computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of the code, while multiple non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors.
Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein, and such computer systems are configured with applicable hardware and/or software that enable the performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that the distributed computer system performs operations described herein and such that a single device does not perform all operations.
Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.
All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
In description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to actions and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system's registers and/or memories into other data similarly represented as physical quantities within computing system's memories, registers or other such information storage, transmission or display devices.
In a similar manner, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transforms that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, a “processor” may be a network device or a MACsec device. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or parallel, continuously or intermittently. In at least one embodiment, the terms “system” and “method” are used herein interchangeably insofar as the system may embody one or more methods, and methods may be considered a system.
In the present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a sub-system, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from a providing entity to an acquiring entity. In at least one embodiment, references may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, processes of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface, or an inter-process communication mechanism.
Although descriptions herein set forth example embodiments of described techniques, other architectures may be used to implement described functionality, and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibilities may be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.
Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.
