Patent Application
20080169866
A bandgap reference circuit is used to generate accurate internal voltages and currents that are independent of the external power supply voltage and temperature. One way to implement such a circuit is to add a voltage that increases with temperature (PTAT) to a voltage that decreases with temperature (CTAT). This is readily implemented by comparing junction voltages of two bipolar transistors that are biased at different current densities. See B. Razavi, “Design of Analog CMOS Integrated Circuits,” pages 377-393, 2001. The drawback of this approach is the finite current bias required to extract this voltage. An ideal circuit would simply store a reference voltage on a zero-leakage capacitor. This would reduce the current consumed by the reference voltage generator to that of the supporting circuits, as shown by B. K. Ahuja, et al., “A Very High Precision 500-nA CMOS Floating-Gate Analog Voltage Reference,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2364-2372, December 2005. Unfortunately, conventional CMOS technology does not have the double poly available in the EEPROM process of Ahuja et al. Moreover, the qualification required to make sure that the capacitor is indeed close to zero leakage is prohibitively long for most fabless companies that are using the reference voltage as only one of several components in a custom circuit or system-on-a-chip (SoC) solution.
The present invention is defined by the claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the embodiments described below provide a combined charge storage circuit and bandgap reference circuit. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap reference circuit and the charge storage circuit. The control circuit is operative to control charging of the charge storage circuit by the output of the bandgap reference circuit and control selection of one of the output of the bandgap reference circuit and an output of the charge storage circuit. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
The embodiments will now be described with reference to the attached drawings.
The following embodiments use a combination of a bandgap reference circuit and a charge storage circuit to lower the average power of the bandgap reference circuit. These embodiments can be implemented with conventional CMOS technology, can achieve lower average current consumption as compared to using a conventional bandgap reference circuit alone (e.g., in one embodiment, less than about 20 nA), and can provide excellent power rejection to Vdd noise. One application of these embodiments is in a mobile device that operates with a battery. To save battery power, the mobile device can be placed in a “standby” mode. However, even when in the standby mode, certain components in the mobile device will require a bandgap voltage, and the bandgap reference circuit will still need to be powered. For example, it may be desired to provide bandgap voltage to a volatile memory (e.g., SRAM) to store an IP address in the standby mode, so that when the mobile device is taken out of standby mode, it can quickly “wake up” and connect to the stored IP address. Accordingly, even though the mobile device is in the standby mode and, therefore, should draw as little battery power as possible, there is still a relatively significant draw on the battery due to the bandgap reference circuit being powered. Other devices, such as, but not limited to, wireless remote controls, can encounter similar problems.
The embodiments described herein use a charge storage circuit in combination with a bandgap reference circuit. The bandgap reference circuit is used to charge the charge storage circuit. When the charge storage circuit attains the desired bandgap reference voltage, the bandgap reference circuit is disable, and the charge storage circuit (instead of the bandgap reference circuit) provides the bandgap voltage to the appropriate components. The bandgap reference circuit can be enabled (periodically or otherwise) to recharge the charge storage circuit as needed. Because the bandgap reference circuit is not continuously powered in this embodiment, this embodiment uses less battery power than implementations where the charge storage circuit is not used.
Turning now to the drawings,
In operation, the control circuit 40 provides an enable signal to the bandgap reference circuit 20 and both an enable signal and a charge signal to the charge storage circuit 30 to charge the charge storage circuit 30 with the output of the bandgap reference circuit 20. When the charge storage circuit 30 is properly charged, the control circuit 40 can disable both the bandgap reference circuit 20 and the comparator 50 and then control the multiplexer 60 to provide the output of the charge storage circuit 30. In this way, the system 10 would provide the desired reference voltage without the current and power consumption needed by system that only uses a bandgap reference circuit.
To ensure that the output of the charge storage circuit 30 is within the proper tolerance for use as a reference, the comparator 50 compares the outputs of the control circuit 40 and the bandgap reference circuit 20. By adjusting the digital fine control of the bandgap reference circuit 20 (BGvar[N:0]) (e.g., by plus or minus 50 or 100 milli-volts), the control circuit 140 can determine whether the charge storage circuit 30 is within the proper tolerance for use as a reference. If there is not enough charge in the charge storage circuit 30, the control circuit 40 can program up the charge storage circuit 30 again. This could be done with several iterations until the desired voltage has been reached. The control circuit 40 can then power down the bandgap reference circuit 20 and the comparator 50 and then select the output of the charge storage circuit 30 with the multiplexer 60 (i.e., by selecting input 0). The control circuit 40 can regularly power up the bandgap reference circuit 20 and the comparator 50 (periodically or otherwise) to check the voltage drooping of the charge storage circuit 30. Furthermore, if the charge storage circuit 30 has very low leakage, the control circuit 40 can reduce the frequency of checking the voltage drooping of the charge storage circuit 30 to reduce the overall power even further.
The bandgap reference circuit 20 can be implemented in any suitable manner, including commonly-used conventional implementations. See, for example, B. Razavi, “Design of Analog CMOS Integrated Circuits,” pages 377-393, 2001; and B. K. Ahuja, et al., “A Very High Precision 500-nA CMOS Floating-Gate Analog Voltage Reference,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2364-2372, December 2005, which are both hereby incorporated by reference. An example of one implementation 70 of the charge storage circuit 30 is shown in
A simple calculation of the time constant of the leakage follows. Assume that a 10 mV voltage variation on Vref can be tolerated before calibration. Assume further that a leakage in the order of 1 pA at room temperature is achievable. By using transistor M1 with dimensions that yield a capacitance of about 0.1 nF, the time is given by:
dt=C dV/I=0.1 e-9×10 e-3/1 e-12=1 s
For the average power consumption, assume that about 100 μA for about 200 μs is needed every time calibration is performed. A calibration performed every second provides an average power of 100 μA×200 e-6/1 s=20 nA. Further reduction can be achieved by using a larger transistor M1 yielding a higher capacitance. The Vdd power supply rejection of supply noise of a passive capacitor to ground is also excellent.
At low temperatures, the diode leakages will generally be lower, enabling even less frequent calibrations. At high temperatures, however, the diode leakages increase, which may require more frequent calibrations. The control circuit 40 can either use a temperature input to decide on the frequency of the calibrations, or it could simply start with frequent calibrations and then reduce the frequency of the calibrations as it learns. Many ultra-low power circuits do not have any high-power circuits that generate heat. Hence, those ultra-low power circuits will benefit from infrequent calibrations, resulting in an extremely-low average power consumption.
An example of another implementation 80 of the charge storage circuit 30 is shown in
Another example of an implementation 90 of the charge storage circuit 30 is shown in
An even simpler variation of this non-volatile storage is shown in circuit 100 in
Having generated an essentially zero-power reference voltage (Vref), a very low power voltage regulator for a chip can be achieved—dominated by the power of the control circuit of the regulator. An example of a regulator 110 is illustrated in
For further improvement, an approximate voltage regulator can be achieved using zero current, as shown in the circuit 130 in
Turning again to the drawings,
Finally, it should be understood that a “circuit,” as that term is used herein, can be implemented in any suitable manner and with any suitable components and should not be limited to any particular type of implementation described herein. A “circuit” can take the form of, for example, a set of basic hardware components (e.g., transistors, resistors, etc.), an application specific integrated circuit (ASIC), a programmable logic controller, an embedded microcontroller, and a single-board computer. Also, while a circuit can be implemented purely with hardware, a circuit can also be implemented with both hardware and software (e.g., a processor running computer-readable program code). Further, one component can be “in communication” with another component directly or indirectly through one or more components named or unnamed herein, either through a physical or wireless medium. Also, an output of one component can be provided as an input to another component when the output is in direct communication with the input or is in indirect communication with the input through one or more components named or unnamed herein, either through a physical or wireless medium.
It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention.
