Patent Application
20060224651
Not Applicable.
Not Applicable.
The present embodiments relate to digital signal processing and are more specifically directed to a combined inverse fast Fourier transform (“IFFT”) and fast Fourier transform (“FFT”) circuit.
Various contemporary digital signal processing circuits and systems require the implementation of IFFT and FFT functionality. For example, orthogonal frequency division multiplexing (“OFDM”) is a multi-carrier frequency system, that is, one where a signal of data bits is sampled into different signals, encoded, and each encoded sample is assigned to a respective sub-carrier frequency; a sample may be of a size selected by one skilled in the art, and by way of example each sample may be one bit wide. Each of the sub-carriers is orthogonal to the others and communicates its respective data signals simultaneously in time with the other carriers. The signal processing in an OFDM transceiver typically includes IFFT and FFT functionality. As another example, contemporary Digital Subscriber Line (“DSL”) modems also implement IFFT and FFT functionality. Still other examples will be ascertainable by one skilled in the art. In various of these applications, IFFT and FFT functions have been implemented by various approaches that are known in the prior art. In general, the IFFT and FFT perform discrete approximations of an inverse Fourier transform and a Fourier transform, respectively. The discrete operations are often performed using a combination of multipliers and adders, so as to perform the known IFFT and FFT equations. One approach for either IFFT or FFT in a Radix 2 implementation is fully serial in nature, that is, for an N-sample transformed output, the serial device operates on one input sample and then combines to provide a result of two samples, and then it combines to provide a result of four samples, continuing in this pattern each time by a power of two until the N-sample output is reached. Another approach for either IFFT or FFT is fully parallel in nature, that is, for an N-sample output, N/2 parallel units each operate on two samples (i.e., two “point”) concurrently to provide a cumulative N-sample result.
While the preceding approaches have proven workable in various prior art implementations, they also may provide various drawbacks, particularly looking to future design criteria. Specifically, in IFFT and FFT circuits, as well as in other signal processing, various criteria are often established for the system design. Such criteria may include considerations of device size, complexity, cost, and speed. A system design must thus efficiently consider such criteria. In this regard, as N in the N-sample output increases, both the fully serial and fully parallel transform approaches have associated drawbacks. For example, in the fully serial implementation, as device speed requirements increase (e.g., in the GHz or higher range), it may not be feasible to provide circuitry, such as multipliers and flip flops, that are capable of operating at such speeds to timely perform the transform. As another example, in the fully parallel operation, such an approach is very gate intensive and, therefore, increases the device size, complexity, and cost. Given these drawbacks as well as others that may be ascertained by one skilled in the art, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.
In one preferred embodiment, there is a system for determining discrete transforms as between time and frequency domains. The system comprises a grid comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an FFT. The system also comprises the integer number of P serially-operating pipelines. Each of the pipelines is coupled to the grid and is operable to perform serially over a number of cycles an integer number S operations of the first transform. In the system, S and P are both greater than one and, in combination, the grid and the serially-operating pipelines perform the first transform type as an S×P-point transform. In a first instance at least a portion of the grid is operable to perform IFFT operations. In a second instance at least a portion of the grid is operable to perform FFT operations.
Other aspects are also disclosed and claimed.
The preferred embodiments are described as implemented into a digital signal processing integrated circuit in an orthogonal frequency division multiplexing (“OFDM”) transceiver system utilizing that circuit. However, it is contemplated that this invention may have benefit in applications other than the specific implementation described in this specification. Accordingly, it is to be understood that the following description is provided by way of example only and is not intended to limit the inventive scope.
Looking now at transceiver 10 in particular, it includes a transmitter path TXP and a receiver path RXP, where both paths in general are known in the art. However, included with these paths is an inverse fast Fourier transform (“IFFT”) and fast Fourier transform (“FFT”) integrated block 12, which is improved per the preferred embodiments and, therefore, also improves the overall transceiver 10. These various improvements are explored later in this document, but prior to reaching that discussion, below is provided a discussion of transmitter path TXP and a receiver path RXP so as to appreciate the overall construction and operation of transceiver 10.
Turning to transmitter path TXP of transceiver 10, it receives information bits Bi from various sources. Bits Bi may be provided by various known types of circuitry and those bits include both user data (e.g., voice, text, or other user-created data) as well as control data. Bits Bi are input to a channel encoder 14. Channel encoder 14 encodes the information bits Bi in an effort to improve raw bit error rate, where various encoding techniques may be used. Preferably, therefore, channel encoder 14 performs forward error correction (“FEC”). Channel encoder 14 also may be changed to use a different coding scheme such as in a Turbo encoder. The encoded output of channel encoder 14 is coupled to the input of an interleaver 16. Interleaver 16 operates with respect to a block of encoded bits and shuffles the ordering of those bits so that the combination of this operation with the encoding by channel encoder 14 exploits the time diversity of the information. For example, one shuffling technique that may be performed by interleaver 16 is to receive bits in a matrix fashion such that bits are received into a matrix in a row-by-row fashion, and then those bits are output from the matrix to a modulator 18 in a column-by-column fashion. As a result, if the SNR of certain bits during transmission falls in level, then when those bits are de-interleaved at the receiver the drop in signal is effectively applied to bits spread at different locations in the data stream rather than concentrated at one location which would thereby render data at that location less discernable. Modulator 18 is in effect a symbol mapper in that it converts its input bits to complex symbols, each designated generally as si. The converted symbols may take various forms, such as quadrature phase shift keying (“QPSK”) symbols, binary phase shift keying (“BPSK”) symbols, or quadrature amplitude modulation (“QAM”) symbols. Note that modulator 18 might operate differently with respect to the user data and the control data and it may operate on the bits with respect to certain modulation parameters. Each symbol si is coupled to a serial-to-parallel converter 20. In response, serial-to-parallel converter 20 receives the incoming symbols and outputs m symbols in a parallel stream, along its outputs 20o1 through 20om, to an inverse fast Fourier transform (“IFFT”) block 22, which is shown as part of integrated block 12. IFFT block 22, as its name suggests, performs an IFFT on samples of the parallel input data, thereby converting the frequency components in the carrier of the signal to the time domain. In the preferred embodiment and as detailed later, a cyclic prefix is also added by block 22. The data in its form as output by IFFT block 22 is referred to in the art as an OFDM symbol, which is not to be confused with each complex symbol si that is provided by modulator 18; indeed, the art also uses other terms for the OFDM symbol such as a burst. For the sake of consistency, in this document the term OFDM symbol is used, and the OFDM symbol as output from IFFT block 22 is connected to a parallel-to-serial converter 24. Parallel-to-serial converter 24 converts its parallel input to a serial output. Thus, the OFDM symbol is now a serial stream of information, and that stream is connected to a radio frequency (“RF”) transmit front end 26, which includes a digital-to-analog converter as well as other analog RF front-end circuitry. The digital-to-analog converter portion converts the digital input to an analog output, and the analog signal is conditioned and passed to an antenna ANT for transmission to a receiver or another transceiver of the form 10 shown in
Turning to receiver path RXP in
where, WN, known in the art as a Twiddle factor, is as shown in the following Equation 2:
WN=e−j2π/N Equation 2
Given the preceding, as shown below, block 12 includes both a parallel component and a number of serial (i.e., “pipeline”) components to achieve the operation of Equation 1.
Looking now to block 12 of
The connectivity of block 60 is now described by way of tracing various examples through its illustrated grid. Looking to sample X[0] as a first example, it is connected from a node N1.1 as an addend to an adder node AN1.1, which also receives sample X[4] as an addend from a node N21. The sum of these two samples is coupled to a node N1.2, from where that sum is connected as an addend input to an adder node AN1.2, which also receives an addend input from a node N3.2. The output of adder node AN1.2 is connected to a node N1.3, from where it is provided as an addend input to adder node AN1.3 and also to an adder node AN5.3. Adder node AN1.3 receives as a second addend input the value from a node N5.3, and the sum determined by adder node AN1.3 is connected to a node N1.4, which provides the transformed sample value, x[0]. Looking to sample X[4] as another example, it illustrates additional connectivity, and certain signals also are shown to incur a multiplication times either a −1 or a Twiddle factor, as is now explored. Sample X[4] is connected from a node N2.1 as an addend input to adder node AN1.1; additionally, sample X[4] is multiplied times −1 and the product is connected as an addend input to adder node AN2.1, which also receives sample X[0] as an addend input from node N1.1. At this point, therefore, note that the connectivity depicted as horizontal and diagonal with respect to samples X[0] and X[4] and adder nodes AN1.1 and AN2.1 is referred to in the art as a butterfly connection or butterfly circuit, where such connection is identified by way of example in
From the preceding and with the skill in the art, one should appreciate the overall operation of block 60 of
Looking to butterfly circuit BF21.2 in additional detail, a second input to butterfly circuit BF21.2 is from a sample collection circuit CL1.2, which collects over successive clock cycles two samples from the upper output 64U1.2 of butterfly circuit BF21.2, with those two samples represented by the “2” in parenthesis adjacent the CL1.2 designation. Thus, in a first initial cycle of operation, butterfly circuit BF21.2 provides outputs at both its upper and lower outputs 64U1.2 and 64L1.2, respectively, with the signal at upper output 64U1.2 being collected by collection circuit CL1.2; in a second clock cycle, butterfly circuit BF21.2 receives a next sample from input 641IN, but in this second clock cycle, a second input is not yet available from collection circuit CL1.2. However, in a third clock cycle, butterfly circuit BF21.1 receives yet another sample from input 641IN, and at this same time with two samples having been collected by collection circuit CL1.2, the first of those two samples, collected two clock cycles earlier, is now provided by that circuit as a second input to butterfly circuit BF21.2, and in response an output is connected as a multiplicand input to a multiplier 64M1.2, which receives a Twiddle factor as its second multiplicand input. This process repeats, so that in a fourth clock cycle, butterfly circuit BF21.2 receives yet another sample from multiplier 64M1.1 and at this same time it receives as an input another sample from collection circuit CL1.2 that was collected by collection circuit CL1.2 two clock cycles earlier. Accordingly, once two samples are collected by collection circuit CL1.2, for each successive clock cycle it provides an input to butterfly circuit BF21.2 that was output by that same circuit two clock cycles earlier.
The preceding connectivity described with respect to butterfly circuits BF21.1 and BF21.2 is comparable for each of the three remaining three stages of butterfly circuits in pipeline 641, with the difference being the number of samples buffered by each collection circuit CL1.3, CL1.4, and CL1.5, which buffer a total of 4, 8, and 16 samples, respectively. Thus: (i) for every clock cycle after four initial clock cycles, collection circuit CL1.3 provides as an input to butterfly circuit BF21.3 a sample that was provided from upper output 64U1.3 four clock cycles earlier; (ii) for every clock cycle after eight initial clock cycles, collection circuit CL1.4 provides as an input to butterfly circuit BF21.4 a sample that was provided from upper output 64U1.4 eight clock cycles earlier; and (iii) for every clock cycle after sixteen initial clock cycles, collection circuit CL1.5 provides as an input to butterfly circuit BF21.5 a sample that was provided from upper output 64U1.5 sixteen clock cycles earlier. Moreover, given this description for pipeline 641 and the numbering conventions in
Having described various IFFT aspects of the preferred embodiments, recall that block 12 is stated earlier to provide both IFFT and FFT functionality. More particularly, while the preceding has demonstrated a 256-point IFFT, further aspects are now described wherein the preferred embodiments also achieve a 128-point FFT. By way of introduction, first re-stated here is Equation 1, which recall pertains to IFFT operations:
Next, by way of comparison, consider that FFT operations cumulatively serve the following known Equation 3:
Comparing Equations 1 and 3, note the following differences: (1) IFFT pertains to frequency samples, while FFT pertains to time samples; (2) the sign of the Twiddle factor exponent is negative for IFFT and positive for FFT; and (3) IFFT involves a scaling of 1/N that is not included in FFT. These differences may be implemented as part of the preferred embodiments such that selected functionality and hardware (e.g., multipliers, adders) of the above-described system also may achieve a 128 point FFT, as is further explored below.
Turning first to the change in input/output for the FFT approach to the preferred embodiments, recall from above that IFFT operates with respect to frequency samples and FFT operates with respect to time samples. Accordingly, per the preferred embodiments, to achieve an FFT operation, time samples x(n) are provided as inputs to parallel IFFT block 60. In this regard, however, note various observations. First, since only a 128-point FFT is desired as opposed to the above-achieved 256-point IFFT, then only half of the inputs are used to implement the FFT functionality. Accordingly, time samples are connected only to inputs 60I1, 60I2, 60I3, and 60I4. In addition, recall from
Looking now to the change in sign of the Twiddle factors as between the IFFT and FFT operations, note that both the butterfly circuits BFFFT as well as pipeline blocks 641, 643, 645, and 647 require multiplication operations using various Twiddle factors. However, the underlying Twiddle factor other than the exponent sign change remains the same. Accordingly, in the preferred embodiment, the same circuit store (e.g., MEM) that provides the IFFT Twiddle factors may again be addressed to provide those values as the FFT Twiddle factors, with the additional consideration that those factors for the FFT have a change in exponent sign. To accomplish an equivalent of the multiplication times the Twiddle factor with a change in its exponent sign, recall that each sample is a complex number; as a result, then a product from the sample times a Twiddle factor that has a sign change in its exponent may be achieved by swapping the Real and Imaginary coefficients of the input sample and then swapping the Real and Imaginary coefficients of the resulting product output. In other words, for a sample of a+jb times a first Twiddle factor, then the product of that same sample times a second Twiddle factor, which is the first Twiddle factor with a sign change in its exponent, may be achieved by multiplying b+ja times the first Twiddle factor and then switching the Real and Imaginary portions of the product result. Because the IFFT with one sign for its Twiddle factors is applied across the grid of parallel IFFT block 60 and pipelines 641 through 648, and the FFT with an opposite sign for its Twiddle factors is applied across a portion of the grid of parallel IFFT block 60 and some of pipelines 641 through 648 as detailed below, then the coefficient swap in the preferred embodiment is only performed at the inputs to block 60 and to the outputs of pipelines 641 through 648. Accordingly, an operation to switch these coefficients may be achieved in various manners, such as using multiplexer or switching circuitry SW2 as shown in
Given the preceding,
Also in connection with the preferred embodiments, still additional features may be implemented for a given application. Thus, below such features are described, and one skilled in the art may appreciate that while each such feature is included in this description, such features may therefore be combined into a singular preferred embodiment application or, alternatively, only a subset of one or more features may be included in different preferred embodiment applications, with the choice from these features as well as others being ascertainable by one skilled in the art.
As another possible preferred embodiment aspect, it is known in certain wireless transmission systems (e.g., OFDM) to include a cyclic prefix with each transmission of a group of symbols. Such a prefix includes a subset of the group of symbols that is copied from the group and prepended in front of the group of symbols. Various techniques and blocks are often implemented to achieve this functionality. In a preferred embodiment, however, such a prefix is incorporated into the IFFT functionality by taking advantage of the exponent of the Twiddle factor. Specifically, consider an example that requires, in addition to the group of samples consisting of the 256-point IFFT, a 64 sample prefix that is the last 64 samples in the 256-point IFFT. In other words, for IFFT samples 0,1,2,3,4, . . . 190,191,192, . . . 253,254,255, the desired sample output is to include a 64 sample prefix so that the total 320 sample output reads as follows: 192,193,194, . . . 254,255,0,1,2, . . . , 253,254,255. Thus, one implementation would be to generate the 256 IFFT samples, await and buffer the last 64 of those samples and then prepend those 64 samples to the sequence of 0,1,2,3,4, . . . , 253,254,255. Such an approach, however, requires waiting for all 256 samples as well as a 64 sample buffer. In contrast, it is recognized in connection with a preferred embodiment that in order to produce a circular shift in the time indices of 64 samples, that a shift in the time domain implies a multiplication at the input of the IFFT by e−j2nπ*64/N=256=e−jnπ/2; accordingly, in a preferred embodiment, to accomplish the circular shift of 64, each input sample is multiplied times e−jnπ/2. With this shift, then in a preferred embodiment, only the first 64 output samples are buffered as they will correspond to samples 192, . . . 253,254,255, and then they are added to the end of the output sequence, following sample 191, to thereby provide the completion of 192, . . . 253,254,255 following the preceding outputs of 192, . . . 253,254,255, . . . 0,1,2, . . . 190, 191. Thus, there is not the need to await the last 64 samples before prepending as was suggested in the approach discussed above.
Note further that the preceding aspect may be implemented in any instance where the rotation length, RL, (e.g., 64) and the total output sample size, TOS, (e.g., 256) have an integer ratio of RL/TOS. In such a case, then the ratio is then multiplied times the exponent of e−j2nπ, giving rise to e−j2nπ*RL/TOS. Moreover, also in the preferred embodiment, with a multiplicand of e−jnπ/2, the functional result may be achieved without an actual multiplier, but instead is more preferably implemented by recognizing that each such multiplication, depending on the value of n, gives rise to a multiplication of only one of eight combinations, that is, of ±1±j, meaning the multiplicand in any given instance is one of 1+j, 1−j, −1+j, −1−j, +1. −1, +j. −j. Thus, in the preferred embodiment, this result is achieved by a sign change of the Real and/or imaginary coefficient, based on the then-corresponding value of n.
As another possible preferred embodiment aspect, recall from Equation 1 that the IFFT operation requires the scaling factor of 1/N while from Equation 3 the FFT operation does not. Accordingly, also in the preferred embodiment the scaling is moved outside of the core architecture of block 12 so that it may be applied only to the IFFT results and not the FFT results.
As a final consideration for various possible preferred embodiment aspects, note that bit sizing for input and output for either the IFFT or FFT operations may be desired. For example, recall that
From the above, it may be appreciated that the preferred embodiments provide a combined IFFT and FFT circuit with various preferred embodiment aspects. In the example provided, a single core is used to achieve both IFFT and FFT operations, which is advantageous in certain applications such as in a transceiver where only the transmit path (e.g., TXP) or the receive path (RXP) is operable at a single time and each path requires one of either the IFFT or FFT operations. Moreover, each of the IFFT and FFT operations are achieved using a combination of P parallel operations achieved via a grid that is coupled to P serially-operating parallel pipelines that each operate to perform S transform operations independently from one another, although under common control so as to achieve proper synchronization. As a result, up to a total of an S×P-point IFFT or FFT operation may be performed. Thus, in the IFFT example given above, P=8 and S=32 for the 256-point IFFT, and for the FFT P=4 and S=32 for the 128-point FFT. However, different preferred embodiments may be derived by choosing different values of S and P, where both S and P are greater than 1 and preferably those values are adjusted for various considerations. For example, in the above-described embodiment, P could be 2 or 4, but is increased to 8 so as to avoid the need for increasing the size and complexity of the parallel grid. In addition, P could be increased if S were reduced, but doing so would increase the need for the faster circuitry that would be required to achieve all of the S serial operations in a sufficient time as dictated by the particular system application. In any event, therefore, the inventive teachings may be applied by one skilled in the art to other size operations as well and the FFT could be the larger point operation as compared to the IFFT operation, in a different embodiment. Still further, a subset of that hardware may be used such that the point-size of the IFFT differs from that of the FFT. Yet further, the two stages could be swapped so that the set of serial pipelines (e.g., 641 through 648) precedes the parallel IFFT block (e.g., block 60). As a result, various advantages and benefits have been shown with respect to the preferred embodiments. For example, a common core may be used to support both the IFFT and FFT operations, as may a single Twiddle memory and address generator for that memory. As another example, a cyclic prefix may be used with a reduced delay. Moreover, one skilled in the art may ascertain still other benefits as well. Thus, the preferred embodiments include various aspects and advantages as compared to the prior art. Accordingly, while the preferred embodiments have been shown by way of example, certain other alternatives have been provided and still others are contemplated. From the above, the preceding discussion and these examples should further demonstrate that while the present embodiments have been described in detail, various substitutions, modifications or alterations could be made to the descriptions set forth above without departing from the inventive scope which is defined by the following claims.
