The present invention relates to the field of communications, and in particular, delay mismatch compensation of data signals received from multiple channels, as well as equalization of the signals simultaneously.
Multiple signals traveling through multiple similar communications channels, e.g. twisted pairs or coaxial cables, experience degradation in signal quality as well as different delays even if the multiple channels have similar physical lengths. This phenomenon is simply shown in
For systems performing signal processing all in digital domain where the analog data signal is sampled and digitized at the receiver front-end by an analog to digital converter (ADC), this delay compensation can be done using digital FIFOs (First In First Out) stages. In system where data processing is done in analog domain, this delay matching must be performed in the analog domain.
Accordingly, what is needed is a system and method that overcomes the above-identified problems. The system and method should be adaptable to existing technologies, easy to implement and cost-effective. The present invention addresses these needs.
A delay compensation technique for two lines or more using multiple sample/hold stages clocked by a multi-phase clock is disclosed. Each line has a delay compensation circuit so as to adjust the delay of the line to match others. Each phase of the clock samples the input data at certain time intervals, T, where the sampling time intervals are typically equal to a symbol period. By selecting and multiplexing the proper sample/hold data to output in each delay compensation circuit, the outcoming samples are aligned within a time interval. The select signal (sel<0:N>) of the multiplexer selects only one sample/hold output at a time and rotates at a frequency of 1/T. The sample/hold stages not selected at the time can be turned off to save power. The outputs from the multiplexers of the multiple lines can be further fine aligned by continuously moving the multiplexer select signal versus the sampling clocks in time.
The delay compensation technique in accordance with the present invention can be combined with a finite impulse response (FIR) filter using rotating tap weights. Combining the filter and the delay stage together has the advantage of limiting the sample/hold stages that the signal needs to go through to one. Also the ON sample/hold stage of the delay compensation circuit in the combined configuration is in fact the FIR stages with rotating tap weights. Therefore in the combination circuit, the delay matching comes at no extra power.
The present invention relates to the field of communications, and in particular, delay mismatch compensation of data signal received from multiple channels, as well as equalization of the signals simultaneously. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
To overcome the drawbacks of the conventional analog delay mismatch cancellation the following design is disclosed. A system and method in accordance with the present invention uses N equal-spaced phases of a clock at 1/N the data symbol rate to obtain the delayed sampled data values, as shown in
The circuit 100 receives a multiphase clock (Clk0-Clkn). The circuit 100 comprises a plurality of sample/hold stages 1060-106n. Each of these stages 101 includes a sampling switch 102 sampled to the input voltage, a hold capacitor 104 coupled to the sampling switch 102 and a buffer 106 coupled to the switch 102 and the capacitor 104. Each of the buffers 1060-106n are coupled together and to a multiplexer 108. The multiplexer 108 provides an output voltage (Vout).
The data samples are sampled with T intervals where in most practical cases T is the symbol time or an integer fraction of that. Therefore the data samples are spaced in time by T steps and each sample stays valid for a period of N*T, provided tracking is performed properly as explanined in the following. In this topology, after initially selecting the proper delay cell to account for the delay mismatch by a N:1 multiplexer 108, the multiplexer's 108 select controls selj rotate at the symbol rate to always connect the correct sampled value to the output as shown. Therefore, although each data sample change every N*T period, the output is always updated at the symbol rate. The major advantage of this topology is that each sampled data value only goes through a single S/H buffer independent of the number of delay stages required, thus there is minimal signal degradation in the sampled analog signals. The clocks used in this scheme are also running at 1/N of the symbol rate, so that saves considerable clocking power.
Another major advantage of this design, as shown in
As shown in a three stage topology, each sampled value is valid for a window of three (3) symbol time, and the select window for each sampled value can slide continuously in this valid window, by as much as two (2) symbol times, to set the required delay at the output. Thus, a delay correction circuit with N sample & hold stages, can provide continuous (N-1) symbol time delay adjustment.
The above topology explained in the two previous figures (i.e.
The combination of the delay adjustment stage and the FIR filter is shown in
A delay compensation technique for two lines or more using multiple sample/hold stages clocked by a multi-phase clock is disclosed. Each line has a delay compensation circuit so as to adjusts the delay of the line to match others. Each phase of the clock samples the input data at certain time intervals, T, where the sampling time intervals are typically equal to a symbol period. By selecting the proper sample/hold data to output in each delay compensation circuit, the outcoming samples are aligned within a time interval.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. The delay correction system can be utilized in a variety of environments. For the system can be utilized in the following systems, systems that utilize twisted pairs, coaxial cables, LATS cable or the like. It should be understood that a system and method in accordance with the present invention could be utilized with a variety of other multiple channel wires and that use would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Number | Date | Country | |
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60540664 | Jan 2004 | US |