Claims
- 1. A method for scheduling computation operations on a very long instruction word processor so as to have an optimal iteration period for a cyclic algorithm comprising of a plurality of computation operations, the method comprising the steps of:
preparing for said algorithm a flow graph wherein each computation operation appears as a separate node, and a plurality of edges represents data dependencies between the separate nodes, transforming the flow graph into machine-readable data for use in an integer linear program, wherein the data expresses equations and constraints associated with the optimal iteration period of the algorithm implemented on a processor having a plurality of types of functional units, determining a minimum iteration period for completion of the computation operations by computing an optimal solution to the integer linear program as a solution of its corresponding linear constraints, and scheduling the computation operations according to the optimal solution provided by the integer linear program.
- 2. The method of claim 1, wherein the minimum iteration period is derived by minimizing an objective function in relation to a plurality of operation precedent constraints, job completion constraints, iteration period constraints and functional unit constraints.
REFERENCE TO RELATED APPLICATION
[0001] The present patent application claims priority benefit of U.S. Provisional Application No. 60/240,151, filed Oct. 13, 2000, titled “COMBINED SCHEDULING AND MAPPING OF DIGITAL SIGNAL PROCESSING ALGORITHMS ON VLIW DSPS,” the content of which is hereby incorporated by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60240151 |
Oct 2000 |
US |