S. Devadas and S. Malik, “A Survey of Optimization Techniques Targeting Low Power VLSI Circuits,” in Proc. Design Automation Conf., pp. 242-247, Jun. 1995. |
A Raghunathan, S. Dey, and N. K. Jha, “Glitch Analysis and Reduction in Register Transfer Level Power Optimization,” in Proc. Design Automation Conf., pp. 331-336, Jun. 1996. |
M. Ohnishi et al., “A Method of Redundant Clocking Detection and Power Reduction at RT Level Design,” in Proc. Int. Symp. Low Power Electronics & Design, pp. 131-136, Aug. 1997. |
J. A. Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction,” IEEE Trans. Computers, vol. 30, pp. 478-490, Jul. 1981. |
L. Benini, et al., “Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 220-232, Mar. 1998. |
S. Hassoun and C. Ebeling, “Architectural Retiming: Pipelining Latency-Constrained Circuits,” In Proc. Design Automation Conf., pp. 708-713, Jun. 1996. |
S. K. Bommu et al., “Retiming-Based Factorization for Sequential Logic Optimization,” ACM Trans. Design Automation Electronic Systems, Aug., 1998. |
M. Aldina, et al., “Precomputation-Based Sequential Logic Optimization for Low Power,” IEEE Trans. VLSI Systems, vol. 2, pp. 426-436, Dec. 1994. |
H. Trickey, “Flamel: A High-Level Hardware Compiler,” IEEE Trans. Computer-Aided Design, vol. 6, pp. 259-269, Mar. 1987. |
A. P. Chandrakasan, et al., “Optimizing Power Using Transformations,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 12-31, Jan. 1995. |
M. S. Lam and R. P. Wilson, “Limits of Control Flow on Parellelism,” in Proc. Annual Symp. Comput. Arch., pp. 46-57, 1992. |
A. Chaterjee and R. Roy, “Synthesis of Low Power Linear DSP Circuits Using Activity Metrics,” In Proc. Intl. Conf. VLSI Design, pp. 255-270, Jan. 1994. |
G. Lakshminarayana and N. Jha, “FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions,” in Proc. Design Automation Conf., pp. 102-107, Jun. 1998. |