COMMON-GATE COMMON-SOURCE TRANSCONDUCTANCE STAGE FOR RF DOWNCONVERSION MIXER

Abstract

In an embodiment, a wireless device receiver chain includes a mixer with a common-gate common-source (CGCS) input stage. Differential signals from an off-chip matching network may be input to the CGCS input stage of the mixer, which downconverts the signals to baseband or some intermediate frequency. The input stage includes a pair of NMOS transistors in a common-gate configuration and a pair of PMOS transistors in a common-source configuration. A potential advantage of the CGCS input stage over the existing CGO transconductance stage configuration is that by adding a common-source stage through the PMOS differential-pair, the transconductance gain is decoupled from the high Q matching network.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a portion of receive chain in the transceiver of a wireless device.

FIG. 2 is a block diagram of a common-gate only (CGO) input stage of the mixer in the receive chain of FIG. 1.

FIG. 3 shows a portion of a receive chain in a transceiver of a wireless device including a common-gate common-source (CGCS) input stage to the mixer.

FIG. 4 illustrates an exemplary CGCS input stage.

FIG. 5 is a block diagram of the signals input and output from the matching network.

Claims

1. A wireless device receiver comprising: a matching network;a mixer; anda common-gate common-source (CGCS) mixer input stage including an input for receiving differential input signals from the matching network,a current source,a common-source stage including transistors coupled to the input and the current source,a common-gate stage including transistors coupled to the input and the common-source stage, andan output coupled to the mixer.

2. The wireless device receiver of claim 1, wherein the CGCS mixer input stage further comprises a plurality of inductors coupled between the input and a ground terminal.

3. The wireless device receiver of claim 1, wherein the common-gate stage comprises a pair of NMOS transistors.

4. The wireless device receiver of claim 3, wherein each NMOS transistor in the common-gate stage includes a drain coupled to the common-source stage, a gate coupled to one of the differential input signals, and a source coupled to another of the differential input signals.

5. The wireless device receiver of claim 1, wherein the common-source stage comprises a pair of PMOS transistors.

6. The wireless device receiver of claim 5, wherein each PMOS transistor in the common-gate stage includes a drain coupled to the common-gate stage, a gate coupled to one of the differential input signals, and a source coupled to the current source.

7. The wireless device receiver of claim 1, wherein an output current from the output of the CGCS mixer input stage satisfies the equation:

8. A common-gate common-source (CGCS) transconductance stage comprising: a current source;a common-source stage including a first pair of transistors including a first transistor having a source coupled to the current source, a drain, and a gate coupled to a first differential input signal, anda second transistor having a source coupled to the current source, a drain, and a gate coupled to a second differential input signal and the gate of the first transistor;a common-gate stage including a second pair of transistors, said second pair of transistors including a third transistor having a drain coupled to the drain of the first transistor, a gate coupled to the first differential input signal, and a source coupled to the second differential input signal, anda fourth transistor having a drain coupled to the drain of the second transistor, a gate coupled to the second differential input signal and the gate of the third transistor, and a source coupled to the first differential input signal;a first output to a mixer coupled between the drains of the first and third transistors; anda second output to the mixer coupled between the drains of the second and fourth transistors.

9. The CGCS transconductance stage of claim 7, further comprising: a first inductor coupled between the source of the third transistor and a ground terminal; anda second inductor coupled between the source of the fourth transistor and the ground terminal.

10. The CGCS transconductance stage of claim 7, wherein the first and second transistors comprise PMOS transistors.

11. The CGCS transconductance stage of claim 7, wherein the third and fourth transistors comprise NMOS transistors.