Common-gate common-source transconductance stage for RF downconversion mixer

Abstract

In an embodiment, a method and apparatus for downconverting a received RF signal in a wireless device where differential signals from an off-chip matching network may be input to a CGCS input stage of a mixer, which downconverts the signals to baseband or some intermediate frequency. The input stage includes a pair of NMOS transistors in a common-gate configuration and a pair of PMOS transistors in a common-source configuration. A potential advantage of the CGCS input stage over the existing CGO transconductance stage configuration is that by adding a common-source stage through the PMOS differential-pair, the transconductance gain is decoupled from the high Q matching network.

Description

BACKGROUND

Wireless communication networks are widely deployed to provide various communication services such as voice, packet data, broadcast, messaging, and so on. Examples of such wireless networks include Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, and Orthogonal FDMA (OFDMA) networks. These wireless networks may also utilize various radio technologies such as Wideband-CDMA (W-CDMA), cdma2000, and Global System for Mobile Communications (GSM).

Wireless devices used in such wireless networks include receiver sections for converting radio frequency (RF) signals received by an antenna to baseband signals for digital processing. FIG. 1 shows a portion of an exemplary receiver chain 100 in a wireless device. Wirelessly transmitted RF signals are received by antenna 102. The RF signals are amplified by an LNA (low noise amplifier) 104. The amplified signals are passed to an RF interstage bandpass filter 106, typically a surface acoustic-wave (SAW) filter, and the filtered signal is passed back to a mixer 108.

The LNA 104 and mixer 108 are typically provided on an integrated circuit (“IC” or “chip”) 110, whereas the bandpass filter 106 is typically provided off-chip. A matching network (MN) 112 may be provided for impedance matching in passing filtered signals from the bandpass filter 106 back to the chip 110. The signals from the matching network 112 are input as differential signals to an input stage 114 of the mixer 108, which downconverts the signal to baseband or some intermediate frequency.

The input stage 114 of the mixer may have a conventional common-gate only (CGO) configuration, as shown in FIG. 2. Differential input signals 202, 204, which are identical but 180° out of phase, from the matching network are provided at the sources of NMOS transistors 206, 208, respectively. The gates of NMOS transistors 206, 208 are coupled through resistors 210, 212, providing the “common-gate” aspect of the circuit. The gate of each NMOS transistor 206, 208 is also cross-coupled to the opposite input signal than that provided to its source. PMOS transistors 220, 222 are connected at their gates through resistors 224, 226 to a constant voltage V_g 228, and connected at their sources to supply voltage V_dd 230. The current generated through each NMOS transistor is due to the input signals at its gate and source. The current through each PMOS transistor is constant due to the constant voltages provided at its gate and source. The total current I_t is the sum of the current through the PMOS transistor and NMOS transistor on each column of the circuit.

For a CGO input stage, in order to achieve high gain, the transconductance g_mn of the NMOS transistors must be relatively large, which requires a matching network with a very high Q matching factor. Consequently, a potential disadvantage for CGO input stage is high sensitivity to input Q matching factor.

SUMMARY

In various embodiments, a method and apparatus for downconverting a received RF signal in a wireless device are disclosed. In an embodiment method, differential signals from an off-chip matching network may be input to a CGCS input stage of a mixer, which downconverts the signals to baseband or some intermediate frequency. The input stage includes a common-gate stage, which may include a pair of NMOS transistors coupled to a differential input at their gates and sources, and a common-source stage, which may include a pair of PMOS transistors coupled to a current source at their sources, the differential inputs at their gates, and the common-gate stage at their drains, and RF choke inductors coupled between the differential input and ground.

A potential advantage of an embodiment method using the CGCS input stage over the existing CGO transconductance stage configuration is that by adding a common-source stage through the PMOS differential-pair, the transconductance gain is decoupled from the high Q matching network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a portion of receive chain in the transceiver of a wireless device.

FIG. 2 is a block diagram of a common-gate only (CGO) input stage of the mixer in the receive chain of FIG. 1.

FIG. 3 shows a portion of a receive chain in a transceiver of a wireless device including a common-gate common-source (CGCS) input stage to the mixer.

FIG. 4 illustrates an exemplary CGCS input stage.

FIG. 5 is a block diagram of the signals input and output from the matching network.

DETAILED DESCRIPTION

FIG. 3 is a block diagram of a portion of a wireless device receiver chain including a mixer with a common-gate common-source (CGCS) input stage according to an embodiment.

RF signals received by antenna 302 are amplified by LNA 304 provided on a chip 303. The amplified signals are passed off-chip to a bandpass filter 306. A matching network 308 provides impedance matching for transmitting the filtered signals 310, 311 back on to chip 303. The differential signals are input to CGCS input stage 312 of mixer 314, which downconverts the signals to baseband or some intermediate frequency.

FIG. 4. is a schematic diagram of the CGCS input stage 312 according to an embodiment. Differential input signals wimx_inp 310 and wmix_inm 311 from the matching network are provided at the sources of NMOS transistors M1406 and M2408, respectively. The differential input signals are 180° out of phase. The gates of NMOS transistors 406, 408 are coupled through resistors 410, 411, providing the “common-gate” aspect of the circuit. The gate of each NMOS transistor 406, 408 is also cross-coupled to the opposite input signal than its source through capacitors 412, 413, respectively. Current is generated through each NMOS transistor in response to the input signals at its gate and source.

PMOS transistors M3420 and M4422 are connected at their gates through resistors 424, 425. The sources of the PMOS transistors are tied to current source 430, providing the “common-source” aspect of the circuit. Like NMOS transistors 306, 408, the gate of each PMOS transistor 420, 422 is cross-coupled to the opposite input signal than its source through capacitors 432, 433, respectively. Current is generated through each PMOS transistor in response to the input signal at its gate and the current provided by current source 320. The total current I_t is the sum of the current through the PMOS transistor and NMOS transistor on each column of the input stage.

Inductors 450 and 451 are coupled between the sources of the NMOS transistors 406 and 408, respectively, and a ground terminal. The inductors operative as RF choke inductors and exhibit high impedance at the operating frequency so that most signal current flow up into the transistors instead of ground during operation.

A potential advantage of the CGCS input stage over the existing CGO transconductance stage configuration is that by adding a common-source stage through the PMOS differential-pair 420, 422, the transconductance gain is decoupled from the high Q matching network 308. FIG. 5 shows the signals at the input and output of the matching network 308. Assuming the matching network 308 is lossless, then:

$\frac{I_{\mathrm{in}}}{I_s}=\sqrt{\frac{R_s}{R_{\mathrm{in}}}}\mathrm{and}\frac{V_{\mathrm{in}}}{V_s}=\sqrt{\frac{R_{\mathrm{in}}}{R_s}}\mathrm{where}{R}_{\mathrm{in}}=\frac{1}{g_{\mathrm{mn}}}$ and g_mn is the transconductance of the NMOS transistors.

Referring back the FIG. 4, the output current I_t of the CGCS input stage 312 is given by the following equation:

$I_t=I_s\sqrt{\frac{R_s}{R_{\mathrm{in}}}}+g_{\mathrm{mp}}{V}_s\sqrt{\frac{R_{\mathrm{in}}}{R_s}}=V_s\frac{1}{\sqrt{R_s}}\left(\sqrt{g_{\mathrm{mn}}}+\frac{g_{\mathrm{mp}}}{\sqrt{g_{\mathrm{mn}}}}\right),$ where g_mp is the transconductance of the PMOS transistors.

for a CGO stage, only the first term, √{square root over (g_mn)}, exists. In order to achieve high gain, the NMOS transconductance g_mn has to be sufficiently large, which in turn requires a very high Q matching network. In practice, providing a matching network with a very high Q factor may be difficult to implement and may increase the cost of external components.

The addition of the common-source stage adds the second term,

$\frac{g_{\mathrm{mp}}}{\sqrt{g_{\mathrm{mn}}}}$ and will compensate for the gain if g_mn is not sufficiently high and also relax the Q matching factor. Intuitively, to get high gain from a CGO transconductance stage, the voltage V_in should be as small as possible, however low Q matching will cause V_in to increase and cause a gain drop from the CGO stage. However, with the addition of the voltage-driven common-stage PMOS differential-pair, the V_in increase may produce more current from the common-source stage and thus compensate the gain loss in the common-gate NMOS stage. This is an advantage of combining common-gate and common-source stages without introducing a power consumption penalty.

In an embodiment, a CGCS input stage for a receiver chain includes NMOS transistors M1406 and M2408 having a width of 300 μm and a length of 0.24 μm, and PMOS transistors M3420 and M4422 having a width of 240 μm and a length of 0.24 μm. The cross-coupled capacitors 412, 413 for the NMOS transistors may be about 6 pF, and cross-coupled capacitors 432, 433 for the PMOS transistors may be about 3 pF. The four resistors 410, 411, 424, and 425 may be about 10 kΩ and the two inductors 450, 451 may be about 9 nH.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the CSCG mixer input stage may be used in a variety of wireless devices having similar receivers, including those designed for use in wireless network systems, wireless local area networks, and/or wireless personal area networks. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A method of downconverting a received radio-frequency (RF) signal in a wireless device, comprising: receiving the RF signal at an antenna in the wireless device;amplifying the received RF signal;filtering the amplified RF signals using a filter having an impedance matching that of a mixer via a matching network;inputting the filtered, amplified RF signals as a differential input signal to a common-gate common-source (CGCS) mixer input stage;mixing the filtered, amplified RF signals to output a downconverted RF signal by: conducting the differential input signal to a common-gate stage and to a common-source stage of the CGCS mixer input stage by conducting the differential input signal to a gate and source of each transistor forming the common-gate stage and to a gate of each transistor forming the common-source stage of the CGCS mixer input stage;conducting a signal from a common current source to a source of each transistor forming the common-source stage of the CGCS mixer input stage; andconducting a signal appearing at a drain of each transistor forming the common-source stage of the CGCS mixer input stage to a corresponding drain of each transistor forming the common-gate stage of the CGCS mixer input stage; andoutputting the downconverted RF signal.

2. The method of downconverting a received radio-frequency (RF) signal in a wireless device as recited in claim 1, wherein the current of the outputted downconverted RF signal satisfies the equation:

3. The method of downconverting a received radio-frequency (RF) signal in a wireless device as recited in claim 1, further comprising: decoupling a transconductance gain of the matching network.

4. A wireless device comprising: means for receiving the RF signal at an antenna in the wireless device;means for amplifying the received RF signal;means for filtering the amplified RF signals using a filter having an impedance matching that of a mixer via a matching network;means for inputting the filtered, amplified RF signals as a differential input signal to a common-gate common-source (CGCS) mixer input stage means for mixing the filtered, amplified RF signals to output a downconverted RF signal comprising: means for conducting the differential input signal to a common-gate stage and common-source stage of the CGCS mixer input stage by conducting the differential input signal to a gate and source of each transistor forming the common-gate stage and to a gate of each transistor forming the common-source stage of the CGCS mixer input stage;means for conducting a signal from a common current source to a source of each transistor forming the common-source stage of the CGCS mixer input stage; andmeans for conducting a signal appearing at a drain of each transistor forming the common-source stage of the CGCS mixer input stage to a corresponding drain of each transistor forming the common-gate stage of the CGCS mixer input stage; andmeans for outputting the downconverted RF signal.

5. The wireless device of claim 4, wherein the current the outputted downconverted RF signal satisfies the equation:

6. The wireless device of claim 4, further comprising: means for decoupling a transconductance gain of the matching network.