1. Field of the Invention
This invention relates generally to difference amplifiers, and more particularly, to methods for improving the common mode rejection characteristic of such amplifiers.
2. Description of the Related Art
Difference amplifiers are typically employed to measure the magnitude of a differential voltage. One common application is that of a current sensing circuit. A shunt resistor having a resistance Rshunt is connected to conduct a current of interest I, and the differential voltage Vshunt that develops across the resistor is measured with a difference amplifier, with I given by Vshunt/R.
A conventional circuit arrangement for sensing a current is shown in
Ideally, Vout varies only with difference voltage VIP−VIN. However, inaccuracies can arise in Vout due to errors resulting from finite rejection of the common-mode voltage
present at nodes IP and IN. In the described current measurement application, Vcm can be many times larger than the input voltage, necessitating a large common mode rejection ratio (CMRR). The CMRR for the circuit of
However, practically, Acm is never zero, and thus degrades common-mode rejection. As defined, for example, in Pallás-Areny et al., “Common Mode Rejection Ratio in Differential Amplifiers”, IEEE Transactions on Instrumentation and Measurement”, vol. 40, no. 4, August 1991, Acm is given by:
Thus, Acm is dominated by resistor mismatch, while the contributions due to the operational amplifier itself can be made negligible by careful design.
Many methods are employed to reduce Acm. Typically, some sort of trimming is performed under a fixed set of conditions; for example, the resistors can be laser trimmed such that common-mode error is reduced. However, such trimming is costly, and is generally less effective when circuit conditions differ from those used during the trimming process.
A common mode rejection calibration scheme for difference amplifiers is presented which addresses the problems noted above, with effective common-mode error reduction provided over a range of common-mode input voltages.
The present common mode rejection calibration scheme is for use with a difference amplifier having an associated signal path. The calibration method requires generating a signal which varies with the common mode voltage (Vcm) of the applied differential voltage, scaling the generated signal, and coupling the scaled signal into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.
Because they are straightforward to add or subtract, the generated and scaled signals are typically currents, with the scaled current being coupled to one or more of the currents conducted by the differential transistor pair of the amplifier's input stage. The method can be used with amplifiers that are referenced to ground or to a negative supply voltage, as well as with amplifiers which are chopper-stabilized.
The method is preferably implemented with a voltage-to-current converter which produces a current (Icm) that varies with Vcm, and a digital-to-analog converter (DAC) which receives current Icm at an input, scales Icm in response to a digital value applied at the DAC's digital input, and provides the scaled current (Icm,s) at its analog output. Current Icm,s is coupled to at least one of the currents conducted by the differential transistor pair, with the coupling and scaling performed so as to reduce the common-mode error.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.
a is a schematic diagram illustrating one possible way in which a compensation current as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
b is a schematic diagram illustrating another possible way in which a compensation current as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
a is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
b is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
c is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
d is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.
A block/schematic diagram illustrating the principles of a common mode rejection calibration scheme per the present invention is shown in
Ideally, R1=R3 and R2=R4, and the gain of the amplifier circuit is equal to the differential gain Adm given by −R2/R1. However, as noted above, a common-mode error can appear in Vout, largely as a result of mismatches between resistances R1 and R3, and/or R2 and R4.
The present common mode rejection calibration scheme reduces this common-mode error. This is accomplished by coupling a signal which varies with Vcm into the amplifier's signal path such that it cancels out the common-mode error. This compensation signal can be a voltage or a current, though a current is preferred as currents are easily added to the signal path of an operational amplifier. For purposes of illustration, the generation of a compensation current is discussed herein.
A compensation current is generated by first generating a current (Icm) which varies with Vcm, scaling Icm, and coupling the scaled current (Icm,s) into the amplifier's signal path by means of the differential transistor pair making up the input stage of A1, such that the common-mode error that would otherwise be present in A1's output is reduced.
Rearranging the expression for Acm shown above to obtain an expression for the common-mode error component (Vcmout) present in the output (Vout) of A1:
where VIP and VIN are the voltages at input nodes IP and IN, respectively. To reduce this error, the present common mode rejection calibration system adds a current (Icm,s) to the signal path to compensate for Vcmout. Assuming Icm,s is coupled to an appropriate point in the signal path, the value of Icm,s needed to compensate for Vcmout is given by:
where gm is the transconductance of the differential transistor pair making up the input stage of the operational amplifier. The amplifier is preferably designed such that gm is reasonably constant over temperature.
This current is applied to the reference input of a digital-to-analog converter (DAC) 102, which also receives a digital value D at its digital inputs. DAC 102 is arranged to scale current Icm in response to digital value D, and to provide the scaled current (Icm,s) at its analog output. Scaled current Icm,s is coupled to the differential transistor pair making up the input stage of amplifier A1, so as to mismatch their respective currents and thereby reduce the common-mode error. Since scaled current Icm,s varies with the common-mode voltage at IP and IN, the error reduction can remain effective over a range of common-mode voltages.
Note that scaling could also be accomplished by varying the values of R5, R6, and/or R7. In this case, DAC 102 could be eliminated, such that the voltage-to-current converter and the scaling circuit are the same circuit, and current Icm becomes the scaled current.
In
One possible implementation of V-I converter 100 is shown in
V-I converter 100 is preferably referenced to VSS, to allow processing of the common mode input signal from a voltage a little above VSS to above VDD. The ratio of R5 and R6 is preferably set to attenuate the input signal so as to minimize the common mode input range of amplifiers A2 and A3.
When implemented as shown in
where SFcm,s is the scaling factor imposed by DAC 102. This reduces to:
In
When arranged as shown in
where SF2 is the scaling factor imposed by DAC 112. To completely remove the VSS term from the transfer function, the scaling factors imposed by DACs 102 and 112 should match.
Subtracting I2,s from Icm,s results in a term proportional to the input common-mode voltage, but independent of VSS:
where SFcm,s=SF2=SF.
To reduce common-mode error, current Icm,s is coupled to the input stage of an operational amplifier. A typical embodiment of such an input stage is shown in
In the simplest configuration, scaled current Icm,s is coupled to one of currents IMP1 and IMP2; it is connected to IMP1 in the exemplary embodiment shown in
When second current I2,s is needed to cancel the common-mode error, it would typically be coupled to one current of the differential transistor pair, with Icm,s coupled to the other pair current. In this case, both DACs 102 and 112 would be adjusted as needed to cancel out the common-mode error. One possible arrangement is shown in
Alternatively, Icm,s and I2,s could be switchably connected to either IMP1 or IMP2 as needed to cancel the common-mode error; this is illustrated in
When arranged as shown in
The gm of the amplifier's input stage is ideally set up to have a temperature coefficient of close to zero. When so arranged, compensation voltage Vcomp is given by:
Compensation currents Icm,s and I2,s can alternatively be coupled into the amplifier's signal path at nodes below the active load. One example is shown in
The present common mode rejection calibration scheme can be employed with difference amplifiers having either a single-ended output, as shown in
The present common mode rejection calibration scheme can also be employed with a chopper-stabilized difference amplifier. This is illustrated in
The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.