BRIEF DESCRIPTION OF FIGURES
The invention may be more fully understood by reference to the detailed description, in conjunction with the following figures:
FIG. 1 illustrates a mesh network which includes a number of network nodes.
FIG. 2 illustrates a schematic of mesh network and node control software.
FIG. 3 shows an example of a type of re-transmission hand shaking.
FIG. 4 shows an example of a type of re-transmission hand shaking.
FIG. 5 shows how simultaneous communication to even a small number of nodes impacts communication on a mesh network.
FIG. 5A shows an inclusion controller used to include a new slave on behalf of the network SIS.
FIG. 6 shows software components of a mesh network split into a slave application and basis software.
FIG. 7 shows controller node software features.
FIG. 8 shows a block diagram of a mesh network node.
FIG. 9 illustrates a block diagram of a transceiver and RF modem.
FIG. 9A and FIG. 9B are waveforms of asymmetric modulation.
FIG. 9C is a block diagram of the Phase-Lock-Loop functionality of the invention.
FIG. 9D is a timing diagram of the sequence for frequency calibration.
FIG. 9E is a waveform of VCO automatic self-calibration.
FIG. 10 illustrates a timing diagram of a pulse width modulated output (PWM).
FIG. 11 shows I/O for a typical application circuit.
FIG. 12 shows external crystal connections.
FIG. 13 shows a simplified block diagram of an internal reset circuit.
FIG. 14 shows the RF connections in a typical application.
FIG. 15 shows a typical RS232 UART application circuit.
FIG. 16 gives a waveform of a serial byte.
FIG. 17 shows external interrupts.
FIG. 18 shows a simplified TRIAC application circuit.
FIG. 19 shows typical TRIAC waveforms.
FIG. 20 shows zero cross detection disturbed by noise.
FIG. 21 shows a masking of zero cross detection.
FIG. 22 shows the timing of a zero cross detect output.
FIG. 23 shows TRIAC fire delay from zero cross detect.
FIG. 24 shows TRIAC fire delay of FIG. 23 with a correction period.
FIG. 25 illustrates an overview of the internal ADC block.
FIG. 26 shows two registers connected as one distributed shift register.
FIG. 27 shows a typical interface application of an EEPROM.
FIG. 28 illustrates a simplified block diagram of a typical interface to programming equipment.
FIG. 29 illustrates a multi-speed demodulator.
FIG. 30 illustrates the potential relations between a media server, media renderer, and control point.
FIG. 31 illustrates a simplified embodiment of a media server, media renderer, and control point combination within a home audio-visual system.