Patent Application
20240089074
The present disclosure relates to a communication apparatus and a communication system.
In a technology having been proposed, a Master SerDes and a Slave SerDes perform high-speed serial communication (see PTL 1).
When audio signals are transmitted between the two SerDeses, signals conforming to the I2 S (Inter-IC Sound) protocol may be transmitted.
However, signals conforming to the I2 S protocol are asynchronous with signals transmitted between two SerDeses, and their frequency bands also are different. In addition, the number of the frequencies of sampling clocks for the audio signals is not necessarily only one, and the frequencies of the sampling clocks are different depending on sound sources, in some cases. It is necessary to make it possible to transmit these audio signals between the two SerDeses and regenerate the audio signals correctly.
In view of this, the present disclosure provides a communication apparatus and a communication system that make it possible to transmit audio signals between communication apparatuses that perform signal transmission asynchronously to the audio signals, and to regenerate the audio signals correctly.
In order to solve the problem described above, the present disclosure provides a communication apparatus including a counting section that counts the number of a predetermined reference clock included in one cycle of a divided signal of an audio master clock with a frequency that is equal to a product of a frequency of a sampling clock for sampling of an audio signal and a multiplier on the basis of the audio master clock, a ratio of division of the divided signal and the predetermined reference clock, and a packet generator that generates a packet including information including the number counted at the counting section, a bit width of SD (Serial Data) conforming to an I2 S standard, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.
The packet generated by the packet generator may include a header portion and a data portion, the header portion may include the number counted at the counting section, the bit width of the SD, the frequency of the sampling clock, the ratio of division, and the frequency ratio, and the data portion may include a plurality of pieces of the SD.
The header portion may include the bit width of the SD, the number of channels of the SD, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, the frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, a frequency of the reference clock, and the number counted at the counting section.
The data portion may include the SD of all channels and all samples.
The communication apparatus may include a physical layer clock generator that generates a clock to be used in common by physical layers of both the communication apparatus and a communication partner apparatus, and a divider that divides the clock generated at the physical layer clock generator and generates the reference clock.
A frequency of the clock generated at the physical layer clock generator may be 250 MHz.
The frequency of the audio master clock may be 25.6 MHz, and the frequency of the sampling clock may be 50 kHz.
The sampling clock and the audio master clock may be asynchronous with the reference clock.
The sampling clock and the audio master clock may be synchronous with the reference clock.
The communication apparatus may include a PTB clock generator that generates a PTB (Precision Time Base) clock to be used to generate timestamp information to be used in common by the communication apparatus and a communication partner apparatus, in which the reference clock may be the PTB clock.
The audio master clock may be synchronous with the PTB clock.
A frequency of the PTB clock may be 250 MHz.
The present disclosure provides a communication apparatus including a counting section that receives a WS (Word Select) signal conforming to an I2 S standard, and counts, on the basis of a predetermined reference clock used in common by the communication apparatus and a communication partner apparatus, first timing information representing a timing of a logical change of the WS signal in a first piece in a plurality of pieces of SD (Serial Data) included in one packet to be transmitted to the communication partner apparatus, and second timing information representing a timing of a logical change of the WS signal in a last piece in the plurality of pieces of SD, and a packet generator that generates the packet including a bit width of the SD, a frequency of a sampling clock for sampling of an audio signal, the first timing information, the second timing information, the number of the pieces of the SD included in the one packet, and the SD.
The packet generator may generate the packet including information regarding the number of channels of the SD.
The present disclosure provides a communication apparatus including a recovering section that receives a packet transmitted from a communication partner apparatus, and recovers, from the packet, SD (Serial Data) conforming to an I2 S standard, a bit width of the SD, a frequency of a sampling clock for sampling of an audio signal, a frequency ratio of a frequency of an audio master clock to the frequency of the sampling clock, the number of a predetermined first reference clock included in one cycle of a divided signal of the audio master clock, the frequency of the sampling clock, and a ratio of division of the divided signal to the audio master clock, an audio master clock regenerator that regenerates the audio master clock on the basis of the number of the first reference clock, a frequency of the first reference clock and the ratio of division, and an SCK regenerator that regenerates an SCK (Serial Clock) on the basis of bit width information regarding the SD, the frequency ratio and the audio master clock.
The communication apparatus may include a clock regenerating circuit that generates a second reference clock synchronous with a signal change of the SD on the basis of the packet, and a frequency ratio calculating section that calculates a frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, in which the audio master clock regenerator regenerates the audio master clock on the basis of the number of the first reference clock, frequency information regarding the first reference clock, the ratio of division and the frequency ratio calculated at the frequency ratio calculating section.
The communication apparatus may include a PTB clock generator that generates a PTB (Precision Time Base) clock to be used to generate timestamp information to be used in common by the communication apparatus and the communication partner apparatus, in which the first reference clock may be the PTB clock.
The present disclosure provides a communication apparatus including a recovering section that receives a packet transmitted from a communication partner apparatus, and recovers, from the packet, SD (Serial Data) conforming to an I2 S standard, bit width information regarding the SD, frequency information regarding an SCK (Serial Clock), first timing information representing a timing of a first logical change of a WS (Word Select) signal included in the one packet, second timing information representing a timing of a last logical change of the WS signal, and the number of pieces of the SD included in the one packet, a clock generator that generates a reference clock to be used in common by the communication apparatus and the communication partner apparatus, a WS signal regenerator that regenerates the WS signal on the basis of the first timing information, the second timing information, the number of the pieces of the SD and the reference clock, an audio master clock regenerator that regenerates an audio master clock with a frequency that is equal to a product of a frequency of the WS signal regenerated at the WS signal regenerator and a multiplier, and an SCK regenerator that regenerates the SCK on the basis of the WS signal regenerated at the WS signal regenerator and the bit width information regarding the SD.
The communication apparatus may include a PTB clock generator that generates a PTB (Precision Time Base) clock to be used to generate timestamp information to be used in common by the communication apparatus and a communication partner apparatus, in which the reference clock may be the PTB clock.
The packet may be transmitted in a period allocated by TDD (Time Division Duplex).
The present disclosure provides a communication system including a first communication apparatus, and a second communication apparatus that performs serial communication with the first communication apparatus, in which the first communication apparatus has a counting section that counts the number of a predetermined reference clock included in one cycle of a divided signal of an audio master clock with a frequency that is equal to a product of a frequency of a sampling clock for sampling of an audio signal and a multiplier on the basis of the audio master clock, a ratio of division of the divided signal and the predetermined reference clock, and a packet generator that generates a packet including information including the number counted at the counting section, a bit width of SD (Serial Data) conforming to an I2 S standard, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD, and the second communication apparatus has a recovering section that receives the packet transmitted from the first communication apparatus, and recovers, from the packet, the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, the number of a predetermined first reference clock included in one cycle of the divided signal of the audio master clock, the frequency of the sampling clock, and the ratio of division of the divided signal to the audio master clock, an audio master clock regenerator that regenerates the audio master clock on the basis of the number of the first reference clock, a frequency of the first reference clock and the ratio of division, and an SCK regenerator that regenerates an SCK (Serial Clock) on the basis of bit width information regarding the SD, the frequency ratio and the audio master clock.
The present disclosure provides a communication system including a first communication apparatus, and a second communication apparatus that performs serial communication with the first communication apparatus, in which the first communication apparatus has a counting section that receives a WS (Word Select) signal conforming to an I2 S standard, and counts, on the basis of a predetermined reference clock used in common by the first communication apparatus and the second communication apparatus, first timing information representing a timing of a logical change of the WS signal in a first piece in a plurality of pieces of SD (Serial Data) included in one packet to be transmitted to the second communication apparatus, and second timing information representing a timing of a logical change of the WS signal in a last piece in the plurality of pieces of SD, and a packet generator that generates the packet including a bit width of the SD, a frequency of a sampling clock for sampling of an audio signal, the first timing information, the second timing information, the number of the pieces of the SD included in the one packet, and the SD, and the second communication apparatus includes a recovering section that receives the packet transmitted from the second communication apparatus, and recovers, from the packet, SD (Serial Data) conforming to an I2 S standard, bit width information regarding the SD, frequency information regarding an SCK (Serial Clock), first timing information representing a timing of a first logical change of a WS (Word Select) signal included in the one packet, second timing information representing a timing of a last logical change of the WS signal, and the number of pieces of the SD included in the one packet, a clock generator that generates a reference clock to be used in common by the second communication apparatus and the first communication apparatus, a WS signal regenerator that regenerates the WS signal on the basis of the first timing information, the second timing information, the number of the pieces of the SD and the reference clock, an audio master clock regenerator that regenerates an audio master clock with a frequency that is equal to a product of a frequency of the WS signal regenerated at the WS signal regenerator and a multiplier, and an SCK regenerator that regenerates the SCK on the basis of the WS signal regenerated at the WS signal regenerator and the bit width information regarding the SD.
Hereinbelow, embodiments of a communication apparatus, a communication system, and a communication method are explained with reference to the figures. Whereas major constituent portions of the communication apparatus and the communication system are mainly explained hereinbelow, there can be undepicted or unexplained constituent portions or functionalities in the communication apparatus and the communication system. The following explanation does not exclude undepicted or unexplained constituent portions or functionalities.
For example, the first communication module 100 and the second communication module 200 can transmit audio signals by using I2 S which is an inter-IC audio signal transmission protocol specified by an FPD-LINK standard, which is one of vehicle-mounted high-speed interface technologies.
Currently, the Automotive SerDes Alliance (ASA) which is a vehicle-mounted high-speed serial interface standardization body is working on standardization of a vehicle-mounted high-speed serial interface technology. The difference between FPD-LINK and ASA is that, while FPD-LINK uses frequency division multiplexing like the one depicted in
The first communication module 100 depicted in
A sound signal (audio signal) obtained by sound-collection at the microphone 110 in the first communication module 100 is input to the I2 S device 120. The I2 S device 120 has an ADC 120-1, an I2 S encoder (I2 S ENC) 120-2, and a clock generator (CLK GEN) 120-3.
The clock generator 120-3 generates an audio sampling clock, an audio serial clock, and an audio master clock (hereinafter, an MCK) in synchronization with a reference clock generated at the X′tal 140.
The ADC 120-1 performs AD conversion of the audio signal from the microphone 110 in synchronization with the audio sampling clock and generates audio data. The I2 S encoder 120-2 encodes the audio data in synchronization with the audio serial clock, and generates an SCK (Serial Clock), a WS (Word Select) signal, and SD (Serial Data) conforming to the I2 S protocol. In the present specification, an SCK, a WS, and SD are collectively referred to as an I2 S signal, in some cases.
The SCK, the WS signal, the SD, and the MCK generated at the I2 S device 120 are input to the SerDes 130. In addition, video data obtained by image-capturing at the camera 150 and a reference clock generated at the X′tal 160 are input to the SerDes 130.
The SerDes 130 generates a packet including the audio data according to the audio signal obtained by sound-collection at the microphone 110 and transmits the packet to the SerDes 230 via the cable 300. The packet is transmitted in a period allocated by TDD. The SerDes 230 receives the packet transmitted from the SerDes 130, recovers the original SCK, WS signal, SD, and MCK, and recovers the video data obtained by image-capturing at the camera 150.
The SCK, WS signal, SD, and MCK recovered at the SerDes 230 are input to the I2 S device (I2 S audio device) 220. The I2 S device 220 has an I2 S decoder (I2 S DEC) 220-1, a DAC 220-2, and a clock divider (CLK divider) 220-3.
The clock divider 220-3 generates an audio sampling clock and an audio serial clock in synchronization with the MCK regenerated at the SerDes 230. The I2 S decoder 220-1 recovers the original audio data in synchronization with the audio serial clock. The recovered audio data is supplied to the DAC 220-2 and the ADAS/ADS processor 260. The DAC 220-2 performs DA conversion of the audio data to generate an audio signal and inputs the audio signal to the speaker 210. Thereby, the audio signal obtained by sound-collection at the microphone 110 is regenerated from the speaker 210. The ADAS/ADS processor 260 performs analysis or the like of the audio data and uses results thereof for recognition of the surrounding environment, for example.
As mentioned above, in the communication system 1 depicted in
Typically, an audio master clock MCK with a frequency which is equal to the product of a sampling frequency fs and the multiplier K is used in a digital sound process. Accordingly, as depicted in
In recent years, audio equipment that provides high sound quality is widely used, and high dynamic range signals are transmitted at high sampling clock frequencies. Accordingly, requirements regarding clock jitter on the regeneration side have been becoming more rigorous. High-quality transmission of audio signals by using a high-speed serial interface technology requires accurate transmission of an MCK with a frequency which is the same as the frequency fs of a sampling clock or is equal to an integer multiple of the frequency fs. However, frequencies used for a high-speed serial interface technology adopted for the SerDes 130 and 230 and the like are frequencies unrelated to the frequencies of sampling clocks (44.1 kHz, 48 kHz, 96 kHz, 192 kHz, etc.) or MCKs (22.5792 MHz, 24.576 MHz, etc.) used in typical audio signal processing. Even if the frequency of a sampling clock used in audio signal processing and a frequency used at a high-speed serial interface are asynchronous with each other, it is necessary to make it possible to regenerate an audio signal transmitted via the high-speed serial interface correctly at the destination of the transmission. However, existing high-speed serial transmission protocols such as FPD-LINK mentioned above do not clearly stipulate a specific procedure for the serial transmission of asynchronous audio signals.
Communication apparatuses and the communication system 1 according to the present disclosure explained below are characterized in that audio signals conforming to the I2 S standard can be transmitted and regenerated correctly in a high-speed serial interface technology, for example, in the ASA standard.
The communication system 1 in
The first communication module 10 has the microphone 110, the I2 S device 120, the SerDes 130, and the X′tal 160. The second communication module 20 includes the speaker 210, the I2 S device 220, and the SerDes 230.
The SerDes 130 is a PHY clock master. That is, the SerDes 130 generates a PHY clock used on the physical layer of the SerDes 130 on the basis of the X′tal 160. On the other hand, the SerDes 230 is a PHY clock follower that operates in synchronization with the PHY clock generated at the SerDes 130. More specifically, the SerDes 130 generates transmission symbols for Down Link by using the PHY clock as a symbol clock, and transmits the transmission symbols to the SerDes 230 via the cable 300. The SerDes 230 regenerates the PHY clock from the received transmission symbols, and decodes the received transmission symbols by using the regenerated PHY clock. Here, a transmission symbol corresponds to the minimum unit of a transmission signal changing interval. The minimum unit is an interval during which one bit is transmitted per one transmission symbol in a case of PAM (Pulse Amplitude Modulation) 2, and is an interval during which two bits are transmitted in a case of PAM4.
As depicted in
The PHY block 130-1 has a Down Link transmitting section (Down Link Tx) 130-1-1, a PHY clock generator (CLK GEN) 130-1-3, and an UP Link receiving section (UP Link Rx) 130-1-2. The LINK block 130-2 has a frame constructor 130-2-1, an OAM (Operation Application Maintenance) section 130-2-3, and a frame deconstructor 130-2-2.
The OAM section 130-2-3 in the LINK block 130-2 generates information obtained by monitoring the control or transmission state of the SerDes 130, and includes the information in the application packet. The frame constructor 130-2-1 generates a container including a container header ((5-2) in
The Link frame generated by the frame constructor 130-2-1 is sent to the Down Link transmitting section 130-1-1 in the PHY block 130-1. Processes by the LINK block 130-2 use a clock with a predetermined frequency synchronous with a symbol clock generated at the PHY clock generator 130-1-3 in the PHY block 130-1.
The Down Link transmitting section 130-1-1 in the PHY block 130-1 adds, to the Link frame, a synchronization signal having a special pattern, and generates a transmission frame ((5-4) in
On the other hand, the PHY clock generator 130-1-3 in the PHY block 130-1 generates a symbol clock ((5-5) in
The Down Link transmitting section 130-1-1 converts the transmission frame into transmission symbols ((5-6) in
Next, a reception process by the receiver-side SerDes 230 is explained. The SerDes 230 in
The PHY block 230-1 has an UP Link transmitting section (UP Link Tx) 230-1-1, a Down Link receiving section (Down Link Rx) 230-1-2, a CDR (Clock Data Recovery) 230-1-3, and a clock divider 230-1-4.
Upon reception of the transmission symbols, the Down Link receiving section 230-1-2 sends the received transmission symbols to the CDR 230-1-3. The CDR 230-1-3 extracts change points of the signal level of the received transmission symbols, and regenerates a symbol clock synchronous with the transmission symbol rate ((5-9) in
The Down Link receiving section 230-1-2 assesses the reception level of the transmission symbols received at appropriate timings in synchronization with the symbol clock regenerated at the CDR 230-1-3. Thereby, the Down Link receiving section 230-1-2 can correctly receive the transmission symbols. The Down Link receiving section 230-1-2 recovers the transmission frame from the transmission symbols. In addition, the Down Link receiving section 230-1-2 identifies the position of the following Link frame by using, as a clue, the synchronization signal (sync) added to the transmission frame.
The clock divider 230-1-4 generates an appropriate symbol clock for an UP Link transmission process by the SerDes 230. The frequency of the symbol clock generated by the clock divider 230-1-4 is 2 GHz or 4 GHz, for example. The clock divider 230-1-4 generates the symbol clock for UP Link in synchronization with the symbol clock of Down Link regenerated at the CDR 230-1-3, and supplies the symbol clock for UP Link to the UP Link transmitting section. In addition, the clock divider 230-1-4 supplies, to the LINK block 230-2, a clock with an appropriate frequency used for a Link frame process at the LINK block 230-2.
The LINK block 230-2 has a frame deconstructor 230-2-2, an OAM section (OAM) 230-2-3 and a frame constructor 230-2-1.
The frame deconstructor 230-2-2 decodes the container header of each container ((5-2) in
The deencapsulator 230-4 decodes the packet header of an application packet ((5-1) in
The signal processing explained thus far is signal processing in which an audio signal obtained by sound-collection at the microphone 110 is converted in accordance with the I2 S protocol at the I2 S device 120 to generate an application packet, the generated application packet is transmitted from the SerDes 130 to the SerDes 230, an I2 S signal is recovered in the SerDes 230, the audio signal is recovered from the I2 S signal at the I2 S device 220, and the sound is output from the speaker 210.
On the other hand, it is also possible to generate an application packet at the SerDes 230 on the basis of a signal from an application connected to the SerDes 230, transmit the application packet to the SerDes 130 through UP Link in a procedure opposite to the procedure described above, and regenerate the signal at an application connected to the SerDes 130.
At this time, symbol clocks used in a process by the UP Link transmitting section 230-1-1 in the SerDes 230 are synchronous with symbol clocks ((5-9) in
The I2 S device 120 depicted in
The encapsulator 130-3 in
The PHY clock generator 130-1-3 has a PLL circuit 130-1-3-1 and a clock divider 130-1-3-2. A reference clock generated at the X′tal 160 is input to the PHY clock generator 130-1-3. The PLL circuit 130-1-3-1 generates a clock synchronous with the reference clock generated at the X′tal 160. The clock divider 130-1-3-2 divides the clock generated by the PLL circuit 130-1-3-1, and generates a PHY clock. The PHY clock is used as a reference clock for transmitting the MCK, in addition to being used in internal processes by the Down Link transmitting section 130-1-1, the UP Link receiving section 130-1-2, and the LINK block 130-2. In
Typically, although this depends on individual manners of implementation, symbol rates of signals transmitted in a Down Link and an UP Link are standardized, and the standardized symbol rates are 2 GHz, 4 GHz, 6 GHz, and 8 GHz, for example, corresponding to transmission speeds. One GHz, 500 MHz, 250 MHz, 125 MHz, 62.5 MHz, and the like that are in a frequency division relation with these symbol rates can be generated easily. Accordingly, in an example explained in the present embodiment, any one of 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz is used as the reference clock TxREFCK.
The first I2 S device 120 is connected with the X′tal 140. The clock generator 120-3 generates a sampling clock 120-3-1, an MCK 120-3-3, and an SCK 120-3-2 in synchronization with a clock generated at the X′tal 140.
The ADC 120-1 converts, into a digital signal, a sound signal (audio signal) obtained by sound-collection at the microphone 110, by using the sampling clock 120-3-1. The I2 S encoder 120-2 converts the digital signal into the I2 S format depicted in
The encapsulator 130-3 stores, on the FIFO 130-3-1, the WS signal and the SD from the I2 S encoder 120-2 in synchronization with the SCK. The I2 S signal in the FIFO 130-3-1 is read out according to a read clock with an appropriate speed, and an application packet is generated at the packet constructor 130-3-4 ((9-3) in
As depicted in
The PMC 130-3-3 counts the TxREFCK for the duration of the interval between start flags output from the MCK divider 130-3-2, and outputs the count value (PMC result value=M) to the packet constructor 130-3-4 (7-3 in
The control registers 130-5 output, to the packet constructor 130-3-4, the bit length of transmitted SD (I2 S audio data) (SD bit width), the number of transmitted audio channels, the frequency (fs frq) of the sampling clock, the multiplier K of the sampling clock (the frequency of the audio master clock MCK, fmck=K×fs frq), the MCK divisor N, and frequency information regarding TxRFECK (TxREFCK INFO).
The packet constructor 130-3-4 stores these pieces of information and the PMC result value M in the packet header ((9-2) in
The bits [7:5] of the first byte in the I2 S header depicted in
As depicted in
The bits [4:3] of the first byte in the I2 S header depicted in
The bits [2:0] of the first byte in the I2 S header depicted in
The bits [7:5] of the second byte in the I2 S header depicted in
The bits [4:0] of the second byte in the I2 S header depicted in
The bits [7:5] of the third byte in the I2 S header depicted in
The bits [4:0] of the third byte in the I2 S header depicted in
The ratio of division N of the audio master clock MCK depends on the frequency Fm (=24.576 MHz, 22.5792 MHz, etc.) of the audio master clock MCK. If it is Fm=24.576 MHz, it is N=1536, and if it is Fm=22.5792 MHz, it is N=7056.
The bit 7 of the fifth byte in the I2 S header depicted in
The bits [3:2] of the fifth byte in the I2 S header depicted in
The I2 S data depicted in
The bits [7:0] of the (m+2+n−1+p)-th byte in the I2 S data depicted in
The bits [7:0] of the (m+n−l+p)-th byte in the I2 S data depicted in
The bits [7:0] of the (m+3+n−l+p)-th byte in the I2 S data depicted in
The bits [7:0] of the k-th byte in the CRC depicted in
Next, the internal configuration of and operation by the SerDes 230 are explained.
The SerDes 230 regenerates the frequency fmck of an MCK generated by the transmitter-side I2 S device 120, and transmits the frequency fmck along with a regenerated I2 S signal (an SCK, a WS signal, and SD) to the I2 S device 220.
The CDR 230-1-3 in the PHY block 230-1 in the receiver-side SerDes 230 extracts change points of the signal level of the received transmission symbols as explained already, and regenerates a symbol clock ((5-9) in
As a reference clock (RxREFCK) for regenerating a regeneration-side I2 S audio master clock MCK, any one of 1 GHz, 500 MHz, 250 MHz, 125 MHz, 62.5 MHz, and the like mentioned above is used. Since which frequency is to be used depends on a manner of implementation, the control registers 230-5 supply information regarding the reference clock (RxREFCK_INFO) to the deencapsulator 230-4 for I2 S signal transmission. Simultaneously, the clock divider 230-1-4 supplies, to the deencapsulator 230-4, the reference clock (RxREFCK) with the frequency specified at the control registers 230-5.
Next, operation by the deencapsulator 230-4 is explained. The frame deconstructor 230-2-2 extracts an application packet ((9-1) in
The packet deconstructor 230-4-1 analyzes the packet header ((9-2) in
The RFECK ratio calculating section 230-4-4 calculates a frequency ratio R (=TxREFCK frequency/RxREFCK frequency) on the basis of the frequency information TxREFCK INFO) regarding the transmitter-side REFCK and the frequency information (RxREFCK INFO) regarding the receiver-side REFCK obtained from the control registers 230-5.
By using the obtained frequency ratio R, the TxREFCK regenerator 230-4-5 multiplies the frequency of the RxREFCK by R if it is R≥1, and divides the RxREFCK by R if it is R<1, to thereby regenerate the TxREFCK synchronous with the RxREFCK. The regenerated TxREFCK has a frequency identical to the frequency of the transmitter-side TxREFCK.
The TxRFECK Divider 230-4-6 divides the TxREFCK supplied from the TxREFCK regenerator 230-4-5 by the PMC result value M acquired at the packet deconstructor 230-4-1, and outputs the divided TxREFCK/M to the MCK regenerator 230-4-7.
By multiplying the TxREFCK/M by the transmitter-side MCK divisor N by using N acquired by the packet deconstructor 230-4-1, the MCK regenerator 230-4-7 regenerates an audio master clock MCK synchronous with the transmitter-side audio master clock MCK. The operation mentioned above is the most important MCK regeneration procedure.
The SCK regenerator 230-4-8 regenerates the SCK by multiplying the cycle of the MCK by the reciprocal of K which is the ratio of the frequency fs frq of the sampling clock and the double of the SD bit width (SDBW).
On the other hand, the packet deconstructor 230-4-1 takes out the packetized SD (audio serial data) ((9-3) in
The SD written in the FIFO 230-4-2 is read out according to the SCK, and supplied to the I2 S encoder 230-4-3.
The I2 S encoder 230-4-3 regenerates the I2 S signal in
The I2 S device 220 converts the I2 S signal into an analog audio signal in synchronization with the MCK, and the audio signal is finally output as a sound at the speaker 210.
By the procedure mentioned above, the frequency information regarding the transmitter-side MCK is transmitted to the receiver side, and the MCK can be regenerated accurately on the receiver side by using a PHY clock synchronous between transmission and reception.
In this manner, in the first embodiment, the SerDes 130 receives the WS signal, the SD, and the SCK conforming to the I2 S standard, and the MCK with a frequency which is equal to the product of the frequency of the SCK and the multiplier, the number of the reference clock TxREFCK included in a predetermined cycle of a divided signal of the MCK is counted, and a packet including the counted number, frequency information regarding the reference clock TxREFCK, the ratio of division N of the divided signal to the MCK, and the frequency ratio K of the frequency of the MCK to the frequency fs of the sampling clock is generated, and is transmitted to the SerDes 230. The SerDes 230 receives the packet mentioned above, and can recover the MCK on the basis of the information described above included in the packet. Therefore, even in a case where the SerDes 130 and the SerDes 230 transmit and receive packets at timings which are asynchronous to an I2 S signal, the SerDes 230 can recover the I2 S signal from the received packets, and regenerate the I2 S signal correctly.
Whereas the I2 S device 120 operates asynchronously to the SerDes 130 in the first embodiment, the I2 S device 120 and the SerDes 130 may operate according to mutually synchronous clocks.
The SerDes 130 according to the second embodiment operates similarly to the SerDes 130 according to the first embodiment, but parameters set by the control registers 130-5 are mutually different.
In this manner, since the I2 S device 120 is caused to operate in synchronization with the reference clock TxREFCK generated at the PHY block 130-1 in the SerDes 130 in the second embodiment, the frequencies of the audio master clock MCK and the TxREFCK can be given an integer-multiple relation. In addition, since the I2 S device 120 generates an I2 S signal in synchronization with a PHY clock that is used in common by the physical layers of the transmitter-side SerDes 130 and the receiver-side SerDes 230 in the second embodiment, it becomes unnecessary to use the X′tal 140 in
The SerDes 130 and the SerDes 230 can manage information regarding mutually synchronous timestamps.
For example, in a case where the SerDes 130 and the SerDes 230 perform high-speed serial communication conforming to the ASA standard, the PTB (Precision Time Base) is defined in the ASA standard. The PTB enables synchronization of time information with 4-nsec resolution by an exchange of packets to serve as the time base between the SerDes 130 and the SerDes 230. The time information in the PTB is synchronized with a clock of 250 MHz (hereinafter, a PTB clock), and this clock is used as a TxREFCK. In this case, since the frequency of the TxREFCK is fixed at 250 MHz, frequency information regarding the TxREFCK does not need to be transmitted to the receiver side. Other information (N, K, etc.) needs to be transmitted to the SerDes 230 by being included in the header of an application packet as in the first embodiment. Similarly, the frequency information regarding an RxREFCK is not necessary also at the SerDes 230.
The PTB clock generator 130-7 and the PTB clock generator 230-6 generate PTB clocks that synchronize the Precision Time Base (PTB) standardized by the ASA standard. The PTB enables synchronization of time information with 4-nsec resolution by an exchange of packets to serve as the time base between the SerDes 130 and the SerDes 230. The PTB clocks of 250 MHz used to generate the PTB information are used as the TxREFCK and the RxREFCK. In this case, since the frequency of the TxREFCK and the RxREFCK is determined as 250 MHz, and the transmitter side and the receiver side generate the PTB clocks with the same frequency, the TxREFCK INFO does not need to be transmitted to the receiver side. In other respects, information and operation are the same as those of the SerDes 130 and the SerDes 230 according to the first embodiment.
In this manner, since the PTB clocks used to generate the PTB information to be used by the SerDes 130 and the SerDes 230 to manage timestamp information are used as the reference clocks TxREFCK and RxREFCK, it becomes unnecessary to transmit information regarding the TxREFCK from the SerDes 130 to the SerDes 230, and regenerate the TxREFCK in the SerDes 230, information to be transmitted and received between the SerDes 130 and the SerDes 230 can be reduced, and the internal configuration of the SerDes 130 and the SerDes 230 can be simplified.
In a fourth embodiment, not only the SerDes 130 and the SerDes 230, but the I2 S device 120 also uses a PTB clock.
Thereby, an I2 S signal (an SCK, SD, a WS signal, and an MCK) generated at the I2 S device 120 can be synchronized with the PTB clock. In addition, the X′tal 140 can be omitted.
A fifth embodiment is characterized in that instead of transmission of frequency information regarding an MCK from the SerDes 130 to the SerDes 230, a WS signal representing the frequency of a sampling clock is transmitted.
The internal configuration of the I2 S device 120 in
The PTB time stampler 130-3-5 is supplied with a WS signal representing the frequency of a sampling clock from the I2 S device 120, and a PTB time with 4-nsec resolution (250 MHz) supplied from a PTB timer 130-8. This PTB time is synchronous with a receiver-side PTB time due to a PTB synchronization process standardized by the ASA standard.
The PTB time stampler 130-3-5 performs sampling of the rising edge of an input WS, that is, almost the center of one sample interval of I2 S data, on the basis of the PTB time with 4-nsec resolution (250 MHz) supplied from the PTB timer 130-8, and supplies the PTB time to the packet constructor 130-3-4.
The packet constructor 130-3-4 obtains SD and WS which are I2 S audio data which is rate-adjusted via the FIFO 130-3-1. The packet constructor 130-3-4 includes the obtained SD in an application packet at a timing specified by the frame constructor (130-2-1) ((19-2), 19-4 in
The packet constructor 130-3-4 includes the number of samples of SD in the header of each application packet (19-4 in
Furthermore, the packet constructor 130-3-4 includes, in the packet header, a TS1 and a TS2 which are PTB times of the first SD and the last SD included in an application packet in PTB times of the rising edges of WS of SD output from the PTB time stampler 130-3-5 (19-4 in
The packet constructor 130-3-4 further obtains the bit length of transmitted SD (I2 S audio data) (SD bit width), the number of transmitted audio channels and the frequency (fs frq) of a sampling clock as reference information from the control registers 130-5, and includes these pieces of information, the TS1, the TS2, and the number of samples in the packet header together.
In this manner, the packet header generated by the packet constructor 130-3-4 has the SD bit width, the number of channels, the frequency fs frq of the sampling clock, the TS1, the TS2, and the number of samples as depicted in
The SD bit width is a bit width of SD (I2 S audio serial data) of each channel. The number of channels is the number of audio channels. For example, in a case where it is the number of channels=2, this means normal stereo. fs frq is the frequency of an audio sampling clock and is 44.1 kHz or 48 kHz, for example. The TS1 is a timing of the rising edge of the WS in the first SD in a plurality of pieces of SD in the packet. The TS2 is a timing of the rising edge of the WS in the last SD in the plurality of pieces of SD in the packet. The number of samples is the number of samples of the SD included in one packet.
In addition, an application packet that follows the packet header includes a plurality of pieces of SD corresponding to all samples. Each piece of SD is serial data specified by a sample number and a channel number. The packet constructor 130-3-4 outputs, to the frame constructor 130-2-1, an application packet (19-4 in
The frame constructor 130-2-1 adds sync for synchronization to a plurality of application packets, and configures a transmission frame, and finally the transmission frame is output to a channel. Since these processes are the same as those in
Next, a receiver-side process is explained. Process operation by the frame deconstructor in the SerDes 230 is similar to those in the first to fourth embodiment.
Process operation by the packet deconstructor 230-4-1 is similar to those in the first to fourth embodiments. The packet deconstructor 230-4-1 acquires the PTB timestamps TS1 and TS2 representing the positions of the rising edges of WS of the first data and the last data of SD of all L samples, and the number of the samples that are included in the packet header of a received application packet, and supplies them to a WS frequency calculating section 230-4-9. The WS frequency calculating section 230-4-9 calculates (TS2−TS1)/(number of samples). A result of this calculation represents the average cycle of the frequencies of audio sampling clocks.
In addition, it is also possible to obtain the cycle of the frequencies of sampling clocks with higher precision by adding together and determining the average of calculation results of (TS2-TS1)/(number of samples) obtained from each of a plurality of packets. The WS frequency calculating section 230-4-9 outputs the obtained cycle to a PTB clock divider 230-4-10.
The PTB clock divider 230-4-10 generates a WS signal by dividing a clock of 250 MHz supplied from the PTB clock 230-6 by the value obtained by the WS frequency calculating section 230-4-9. The frequency of the WS signal is the same as the frequency of the sampling clock.
The MCK regenerator 230-4-7 regenerates an audio master clock MCK necessary for processes at the I2 S device 220 by multiplying the WS signal generated at the PTB clock divider 230-4-10 by the constant K by using K obtained by the control registers 230-5.
Furthermore, the SCK regenerator 230-4-8 regenerates an SCK by setting the cycle of the SCK to a cycle obtained by multiplying the cycle of the WS signal by an SD bit width and 2. In synchronization with this SCK, the SD is read out from the FIFO 230-4-2, and the SD having been read out is encoded at the I2 S encoder 230-4-3. Since processes performed at the I2 S encoder 230-4-3 and thereafter are similar to those performed in the SerDes 230 according to the first to fourth embodiments, explanations thereof are omitted.
Since
The bits [7:5] of the first byte and the second byte in the I2 S header depicted in
The bits [7:0] of the third byte in the I2 S header depicted in
The bits [7:0] of the sixth byte in the I2 S header depicted in
The bits [7:0] of the ninth byte in the I2 S header depicted in
Note that setting information that is included as values included in the packet headers depicted in
Furthermore, the application packets ((9-1) in
In this manner, since the timing TS1 of the rising edge of the WS signal in the first SD in a plurality of pieces of SD in an application packet, the timing TS2 of the rising edge of the WS signal in the last SD in the plurality of pieces of SD, and the number of samples of the SD are included in a packet header in the fifth embodiment, the average cycle of the frequencies of sampling clocks can be calculated, and a WS signal can be generated on the basis of a result of the calculation. Therefore, the fifth embodiment eliminates the necessity for transmitting an MCK from the transmitter-side SerDes 130 to the receiver-side SerDes 230 and for counting the number of the reference clock TxREFCK included in a divided signal of the MCK in the SerDes 230 unlike the first to fourth embodiments, and accordingly can simplify the configuration in the SerDes 230.
Note that the present technology may be implemented in the following configurations.
(1)
A communication apparatus including:
The communication apparatus according to (1), in which
The communication apparatus according to (2), in which
The communication apparatus according to (3), in which
The communication apparatus according to any one of (1) to (4), including:
The communication apparatus according to (5), in which
The communication apparatus according to (6), in which
The communication apparatus according to any one of (1) to (7), in which
The communication apparatus according to any one of (1) to (7), in which
The communication apparatus according any one of (1) to (4), including:
The communication apparatus according to (10), in which
The communication apparatus according to (10) or (11), in which
A communication apparatus including:
The communication apparatus according to (13), in which
A communication apparatus including:
The communication apparatus according to (15), including:
The communication apparatus according to (15) or (16), including:
A communication apparatus including:
The communication apparatus according to (14) or (18), including:
The communication apparatus according to any one of (1) to (19), in which
A communication system including:
A communication system including:
Aspects of the present disclosure are not limited to the individual embodiments mentioned above and cover various modifications that can be conceived of by those skilled in the art, and advantages of the present disclosure also are not limited to the content mentioned above. That is, various types of addition, change and partial deletion are possible within the scope not departing from the conceptual idea and gist of the present disclosure derived from the content stipulated in claims and equivalents thereof.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/004160 | 2/3/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63148022 | Feb 2021 | US |
