Patent Application
20160266846
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-49796, filed on Mar. 12, 2015, the entire contents of which are incorporated herein by reference.
Embodiments of the present invention relate to a communication apparatus and a memory control method.
Conventionally, as one of wireless communication techniques, Near Field Communication has been known. For example, in the TransferJet®, by holding a device of its own over a counterpart device, to which it is desired to transfer data, the data can be transferred to the counterpart device, while omitting complicated setting unique to the wireless communication.
However, in the conventional wireless communication techniques, it has been difficult to transfer data (that is, to perform data communication) quickly, while suppressing a delay due to processing other than the data transfer.
A communication apparatus according to an embodiment comprises a transmission device and a controller. The controller writes transmission data to be transmitted to a communication counterpart apparatus in a buffer memory in which the transmission data is written. The transmission device reads the transmission data from the buffer memory and transmits the transmission data to the communication counterpart apparatus. The transmission device outputs a first interrupt signal to the controller in response to transmission completion of the transmission data. The controller can perform a first write process in which the controller confirms a state of the buffer memory in response to the first interrupt signal, and if the buffer memory has a free space where next transmission data can be written, writes the next transmission data in the buffer memory. The controller can perform a second write process in which the controller confirms the state of the buffer memory in response to completion of the first write process, and if the buffer memory has the free space, writes the next transmission data in the buffer memory. The controller performs a new one of the first write process after having performed write of the transmission data in the second write process.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.
The communication apparatus 10 is incorporated in a portable electronic apparatus, for example, a mobile phone, a smartphone, a tablet terminal, a laptop computer, and a digital camera. The communication apparatus 10 can be incorporated in a fixed electronic apparatus, for example, a desktop computer, a server, or an image reproduction apparatus.
The communication apparatus 10 can be an adapter detachably connected to a connector (for example, a USB connector) of, for example, the electronic apparatus. A mode of the communication apparatus 10 is not limited to those described above, and for example, the communication apparatus 10 can be undetachably incorporated in the electronic apparatus. The counterpart terminal 100 can be a portable or fixed terminal, and can be equipped with a communication apparatus similar to the communication apparatus 10.
As shown in
The transmitter/receiver 111 performs data communication with the counterpart terminal 100, for example, by the Near Field Communication. A mode of the Near Field Communication can be such that a high frequency signal is transmitted and received by electric field coupling, for example, between a coupling electrode of the transmitter/receiver 111 and a coupling electrode of the counterpart terminal 100. The Near Field Communication can be, for example, the TransferJet.
Transmission data to be transmitted to the counterpart terminal 100 is written in the buffer memory 112. Reception data received from the counterpart terminal 100 is also written in the buffer memory 112.
The transmitter/receiver 111 reads the transmission data from the buffer memory 112 and transmits the transmission data to the counterpart terminal 100. Further, the transmitter/receiver 111 receives the reception data from the counterpart terminal 100 and writes the reception data in the buffer memory 112.
The controller 12 writes the transmission data in the buffer memory 112. Further, the controller 12 reads the reception data from the buffer memory 112.
The controller 12 can access the transmitter/receiver 111 asynchronously to write the transmission data in the buffer memory 112 via the transmitter/receiver 111 (or by controlling the transmitter/receiver 111). Further, the controller 12 can access the transmitter/receiver 111 asynchronously to read the reception data from the buffer memory 112 via the transmitter/receiver 111 (or by controlling the transmitter/receiver 111).
The transmitter/receiver 111 outputs a first interrupt signal permitting write of the next transmission data to the controller 12 in response to transmission completion of the transmission data. Further, the transmitter/receiver 111 outputs a second interrupt signal permitting read of the next reception data to the controller 12 in response to reception completion of the reception data.
The controller 12 can selectively perform a first write process and a second write process. The first write process here is a process in which a state of the buffer memory 112 is confirmed in response to the first interrupt signal, and if the buffer memory 112 has a free space where the next transmission data can be written, the next transmission data is written N1 times (at least once) in the buffer memory 112. However, N1 is a natural number (the same applies hereinafter). N1 times can be, for example, once. The second write process is a process in which the state of the buffer memory 112 is confirmed in response to completion of the first write process, and if the buffer memory 112 has a free space, the next transmission data is written in the buffer memory 112. Completion of the first write process means that the transmission data has been actually written in the buffer memory 112 by the first write process. Completion of the first write process can be also said to be completion (success) of write of the transmission data by the first write process. Therefore, if the transmission data cannot be written in the buffer memory 112 because there is no free space, the first write process has not been completed yet. As described above, the second write process is started upon completion of the first write process, while the first write process is started upon reception (input) of the first interrupt signal. Therefore, in the second write process, reception of the first interrupt signal can be omitted.
The first write process is also a process in which the next transmission data is not written in the buffer memory 112, if the buffer memory 112 does not have a free space, in the confirmation of the state of the buffer memory 112 in response to the first interrupt signal. Further, the second write process is also a process in which the next transmission data is not written in the buffer memory 112, if the buffer memory 112 does not have a free space, in the confirmation of the state of the buffer memory 112 in response to completion of the first write process.
Transmission of transmission data by the second write process can be a polling process.
The controller 12 performs a new one of the first write process, after write of transmission data by the first or second write process has been performed N2 times in total. However, N2 is a natural number equal to or larger than N1 (the same applies hereinafter). For example, the controller 12 can perform write of transmission data by the first write process once, and then can perform the new first write process after write of transmission data by the second write process has been performed N2-1 times.
If data transmission depending on only the first write process is to be performed, the controller 12 cannot write transmission data in the buffer memory 112, until the first interrupt signal is received from the transmitter/receiver 111. Therefore, transmission of the transmission data is delayed because the transmission data cannot be written in the buffer memory 112. On the other hand, according to the present embodiment, the second write process that does not require reception of the first interrupt signal can be performed, and thus the transmission data can be transmitted quickly. That is, transmission throughput can be improved.
On the other hand, if data transmission depending on only the second write process is to be performed, the controller 12 needs to confirm the state of the buffer memory 112 all the time for the second write process, and thus tasks other than write of the transmission data cannot be executed. Therefore, if data transmission depending on only the second write process is to be performed, execution of other tasks will be delayed. On the other hand, according to the present embodiment, the process can be switched to the first write process after the second write process. Accordingly, the delay of execution of other tasks can be suppressed (reduced).
N2 times can be either constant or variable.
For example, in the controller 12, a transmission frame, whose transmission has been requested from a high order layer, may be divided into a plurality of packets and sequentially transmitted as data (transmission data) in a unit of packet. When the transmission frame is to be transmitted in a unit of packet, N2 times can be the number of write of transmission data required for transmission completion of the entire transmission frame. In this case, the controller 12 can set N2 times based on information relating to the number of transmission packets in a header of the transmission frame. By setting N2 times as the number of write required for transmission completion of the entire transmission frame, the transmission frame can be transmitted quickly.
Further, when the confirmation of the state of the buffer memory 112 has been performed N3 times, if the buffer memory 112 does not have a free space in all the confirmations performed N3 times, the controller 12 can perform a new one of the first write process without performing the second write process. However, N3 is a natural number equal to or larger than N1 (the same applies hereinafter).
If the buffer memory 112 does not have a free space continuously, an execution opportunity of other tasks can be ensured by omitting the second write process and shifting to the first write process. Further, because the second write process can be omitted according to a confirmation result of the state of the buffer memory 112, a process of acquiring the transmission throughput can be omitted. On the other hand, because an opportunity of confirming the free space of the buffer memory 112 can be ensured plural times, the controller 12 can wait for an opportunity to transmit transmission data quickly in the second write process.
The controller 12 can acquire the transmission throughput of the transmitter/receiver 111 and set (change) N3 times according to the transmission throughput.
For example, if the transmission throughput is high, the transmission data written in the buffer memory 112 can be transmitted immediately. In other words, if the transmission throughput is high, it can be said that there is a low possibility that the previous transmission data remains in the buffer memory 112 at the time of write of the transmission data. Because the previous transmission data does not remain in the buffer memory 112, the next transmission data can be immediately written in the buffer memory 112. Therefore, when the transmission throughput is higher than a first transmission threshold, the controller 12 can set N3 times to N1+1 times. N1+1 times can be, for example, twice. In a state where the transmission throughput is high, by setting the number of confirmations of the buffer memory 112 to N1+1 times, transmission data can be transmitted quickly and reliably, and the execution opportunity of other tasks can be ensured promptly.
On the other hand, if the transmission throughput is low, it can be said that there is a high possibility that the previous transmission data remains in the buffer memory 112 at the time of write of the transmission data. Because the previous transmission data remains in the buffer memory 112, the next transmission data cannot be written in the buffer memory 112 immediately. Therefore, when the transmission throughput is lower than a second transmission threshold, which is lower than the first transmission threshold, the controller 12 can set N3 times to N1 times. Setting N3 times to N1 times means also performing a new one of the first write process without performing the second write process. In a state where the transmission throughput is low, by avoiding the useless second write process having a low success rate, the execution opportunity of other tasks can be ensured promptly.
Furthermore, the controller 12 basically sets N2 times to the number of write of transmission data required for transmission completion of the entire transmission frame, and exceptionally, if the transmission throughput is lower than the second transmission threshold, can set (change) N2 times to N1 times. By setting N2 times to N1 times, even if write by the first write process is successful, the next write process does not become the second write process, but becomes a new one of the first write process. Accordingly, an unstable write process (frame transmission) in a state where the transmission throughput is low is interrupted, thereby enabling to ensure the execution opportunity of other tasks promptly.
Further, the controller 12 can selectively perform a first read process and a second read process. The first read process here is a process in which the state of the buffer memory 112 is confirmed in response to the second interrupt signal, and if the buffer memory 112 has the next reception data, the next reception data is read from the buffer memory 112 N4 times (at least once). However, N4 is a natural number (the same applies hereinafter). N4 times can be, for example, once. The second read process is a process in which the state of the buffer memory 112 is confirmed in response to completion of the first read process, and if the buffer memory 112 has the next reception data, the next reception data is read from the buffer memory 112. Completion of the first read process means that the reception data has been actually read from the buffer memory 112 by the first read process. Completion of the first read process can be said to be completion (success) of read of the reception data by the first read process. Therefore, if the reception data cannot be read from the buffer memory 112 because there is no reception data in the buffer memory 112, the first read process has not been completed yet. As described above, the second read process is started upon completion of the first read process, while the first read process is started upon reception (input) of the second interrupt signal. Therefore, in the second read process, reception of the second interrupt signal can be omitted.
The first read process is also a process in which the next reception data is not read from the buffer memory 112, if the buffer memory 112 does not have the next reception data, in the confirmation of the state of the buffer memory 112 in response to the second interrupt signal. Further, the second read process is also a process in which the next reception data is not read from the buffer memory 112, if the buffer memory 112 does not have the next reception data, in the confirmation of the state of the buffer memory 112 in response to completion of the first read process performed N4 times.
Reception of reception data by the second read process can be a polling process.
The controller 12 performs a new one of the first read process, after read of reception data by the first or second read process has been performed N5 times in total. However, N5 is a natural number equal to or larger than N4 (the same applies hereinafter). For example, the controller 12 can perform read of reception data by the first read process once, and then can perform the new first read process after read of reception data by the second read process is performed N5−1 times.
If data reception depending on only the first read process is to be performed, the controller 12 cannot read reception data from the buffer memory 112, until the second interrupt signal is received from the transmitter/receiver 111. Therefore, reception of the reception data is delayed because the reception data cannot be read from the buffer memory 112. On the other hand, according to the present embodiment, the second read process, that does not require reception of the second interrupt signal can be performed, and thus the reception data can be received quickly. That is, reception throughput can be improved.
On the other hand, if data reception depending on only the second read process is to be performed, the controller 12 cannot execute other tasks during the second read process, and thus execution of other tasks is delayed. On the other hand, according to the present embodiment, after the second read process, the process can be switched to the first read process. Accordingly, the execution delay of other tasks can be suppressed (reduced).
N5 times can be either constant or variable.
For example, in the controller 12, a reception frame may be sequentially received one by one for reception data in a unit of packet. When the reception frame is to be received in a unit of packet, N5 times can be the number of read of reception data required until the last reception data in the reception frame has been read from the buffer memory 112. In this case, the controller 12 can set N5 times based on information relating to the number of reception packets in a header of the reception frame. By setting N5 times as the number of read required until the last reception data in the reception frame has been read, the reception frame can be received quickly.
Further, when the confirmation of the state of the buffer memory 112 has been performed N6 times, if the buffer memory 112 does not have the next reception data in all the confirmations performed N6 times, the controller 12 can perform a new one of the first read process without performing the second read process. However, N6 is a natural number equal to or larger than N4 (the same applies hereinafter).
If the buffer memory 112 does not have the next reception data continuously, the execution opportunity of other tasks can be ensured by omitting the second read process and shifting to the first read process. Further, because the second read process can be omitted according to a confirmation result of the state of the buffer memory 112, a process of acquiring the reception throughput can be omitted. On the other hand, because the opportunity of confirming the next reception data in the buffer memory 112 can be ensured plural times, the controller 12 can wait for an opportunity to receive reception data quickly in the second read process.
The controller 12 can acquire the reception throughput of the transmitter/receiver 111 and set (change) N6 times according to the reception throughput.
For example, if the reception throughput is high, after the reception data has been read from the buffer memory 112, the next reception data can be received immediately and written in the buffer memory 112. Because the next reception data has been written in the buffer memory 112, the next reception data can be read from the buffer memory 112 immediately. Therefore, if the reception throughput is higher than a first reception threshold, the controller 12 can set N6 times to N4+1 times. N4+1 times can be, for example, twice. In a state where the reception throughput is high, by setting the number of confirmations of the buffer memory 112 to N4+1 times, reception data can be received quickly and reliably, and the execution opportunity of other tasks can be ensured promptly.
On the other hand, if the reception throughput is low, it can be said that there is a low possibility that after the reception data has been read from the buffer memory 112, the next reception data is received immediately and written in the buffer memory 112. Therefore, when the reception throughput is lower than a second reception threshold, which is lower than the first reception threshold, the controller 12 can set N6 times to N4 times. Setting N6 times to N4 times means performing a new one of the first read process without performing the second read process. In a state where the reception throughput is low, by avoiding the useless second read process having a low success rate, the execution opportunity of other tasks can be ensured promptly.
Further, the controller 12 basically sets N5 times to the number of read of reception data required until the last reception data in the reception frame has been read, and exceptionally, if the reception throughput is lower than the second reception threshold, can set (change) N5 times to N4 times. By setting N5 times to N4 times, even if read by the first read process is successful, the next read process is not the second read process, but a new one of the first read process. Accordingly, an unstable read process (frame reception) in a state where the reception throughput is low is interrupted, thereby enabling to ensure the execution opportunity of other tasks promptly.
An example of a transmission operation of the communication apparatus 10 having the configuration as shown in
As shown in
Next, the controller 12 acquires the transmission throughput (Step S2).
The controller 12 then sets N3 times according to the transmission throughput (Step S3).
The controller 12 confirms the state of the buffer memory 112, that is, the free space thereof (Step S4). At this time, the controller 12 increments the number of memory state confirmations j and sets it to j+1.
Subsequently, the controller 12 determines whether the buffer memory 112 has the free space (Step S5). If the buffer memory 112 has the free space (YES at Step S5), the controller 12 writes the next transmission data in the buffer memory 112 (Step S6). At this time, the controller 12 increments the number of write of transmission data i and sets it to i+1. If the write of the next transmission data (Step S6) is performed in the first round, it is the write in the first write process. If the write of the next transmission data (Step S6) is performed in the second round or more, it is the write in the second write process.
On the other hand, if the buffer memory 112 does not have the free space (NO at Step S5), the controller 12 determines whether the number of memory state confirmations j has reached N3 times (Step S9). If the number of confirmations j has reached N3 times (YES at Step S9), the controller 12 releases the interrupt mask (Step S8). After release of the interrupt mask (Step S8), the controller 12 performs a new one of the first write process. On the other hand, if the number of confirmations j has not reached N3 times (NO at Step S9), the controller 12 confirms the state of the buffer memory 112 again, and increments the number of confirmations j (Step S4).
After write of the next transmission data (Step S6), the controller 12 determines whether the frame transmission is complete or the number of write of transmission data i has reached N2 times (Step S7). If the frame transmission is complete or the number of write of transmission data i has reached N2 times (YES at Step S7), the controller 12 releases the interrupt mask (Step S8). On the other hand, if the frame transmission is not complete and the number of write of transmission data i has not reached N2 times (NO at Step S7), the controller 12 confirms the state of the buffer memory 112 again (Step S4). If the confirmation of the state of the buffer memory 112 is performed in the second round or more, the confirmation is performed in the second write process.
An example of a reception operation of the communication apparatus 10 having the configuration as shown in
As shown in
Next, the controller 12 acquires the reception throughput of the transmitter/receiver 111 (Step S20).
The controller 12 then sets N6 times according to the reception throughput (Step S30).
The controller 12 then confirms the state of the buffer memory 112, that is, the presence of the next reception data (Step S4). The controller 12 then increments the number of memory state confirmations j and determines whether the buffer memory 112 has the next reception data (Step S50).
If the buffer memory 112 has the next reception data (YES at Step S50), the controller 12 reads the next reception data from the buffer memory 112 (Step S60). At this time, the controller 12 increments the number of read of reception data i and sets it to i+1. If the read of the next reception data (Step S60) is performed in the first round, it is the read in the first read process. If the read of the next reception data (Step S60) is performed in the second round or more, it is the read in the second read process.
On the other hand, if the buffer memory 112 does not have the next reception data (NO at Step S50), the controller 12 determines whether the number of memory state confirmations j has reached N6 times (Step S90). If the number of confirmations j has reached N6 times (YES at Step S90), the controller 12 releases the interrupt mask (Step S8). After release of the interrupt mask (Step S8), the controller 12 performs a new one of the first read process. On the other hand, if the number of confirmations j has not reached N6 times (NO at Step S90), the controller 12 confirms the state of the buffer memory 112 again, and increments the number of confirmations j (Step S4).
After read of the next reception data (Step S60), the controller 12 determines whether the frame reception is complete or the number of read of reception data i has reached N5 times (Step S70). If the frame reception is complete or the number of read of reception data i has reached N5 times (YES at Step S70), the controller 12 releases the interrupt mask (Step S8). On the other hand, if the frame reception is not complete and the number of read of reception data i has not reached N5 times (NO at Step S70), the controller 12 confirms the state of the buffer memory 112 again (Step S4). If the confirmation of the state of the buffer memory 112 is performed in the second round or more, the confirmation is performed in the second read process.
Furthermore, in the first write process state (S_2), if the first write process is complete, the controller 12 shifts to a second write process state (S_3).
Further, in the second write process state (S_3), if the total number of write has not reached N2 times, the controller 12 maintains the second write process state (S_3). If the buffer memory 112 does not have a free space and the number of state confirmations of the buffer memory 112 has not reached N3 times, the controller 12 also maintains the second write process state (S_3).
On the other hand, in the second write process state (S_3), if the frame transmission is complete, the controller 12 shifts to the standby state (S_1). If the total number of write has reached N2 times, the controller 12 also shifts to the standby state (S_1). If the number of state confirmations of the buffer memory 112 has reached N3 times, the controller 12 also shifts to the standby state S_1).
Furthermore, as shown in
Further, in the first read process state (S_4), if the first read process is complete, the controller 12 shifts to a second read process state (S_5).
Further, in the second read process state (S_5), if the total number of read has not reached N5 times, the controller 12 maintains the second read process state (S_5). If the buffer memory 112 does not have the next reception data and the number of state confirmations of the buffer memory 112 has not reached N6 times, the controller 12 also maintains the second read process state (S_5).
On the other hand, in the second read process state (S_5), if the frame transmission is complete, the controller 12 shifts to the standby state (S_1). Further, if the total number of read has reached N5 times, the controller 12 also shifts to the standby state (S_1). If the number of state confirmations of the buffer memory 112 has reached N6 times, the controller 12 also shifts to the standby state (S_1).
The controller 12 shifts to the standby state, thereby enabling to execute tasks other than write and read with respect to the buffer memory 112.
If it is desired to give a priority to data transmission over reduction of the delay in execution of other tasks, N3 times can be increased with a decrease of the transmission throughput. Further, if it is desired to give a priority to data reception over reduction of the delay in execution of other tasks, N6 times can be increased with a decrease of the reception throughput.
As described above, according to the present embodiment, by selectively performing the first write process and the second write process, both the improvement of promptness of data transmission and the suppression of the delay in other processes can be achieved. Further, according to the present embodiment, by selectively performing the first read process and the second read process, both the improvement of promptness of data reception and the suppression of the delay in other processes can be achieved. That is, according to the present embodiment, both the improvement of promptness of data communication and the suppression of the delay in processes other than data communication can be achieved.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-049796 | Mar 2015 | JP | national |
