BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic for explaining a conventional parallel computer and issues concerning a synchronization process;
FIG. 2 is a functional block diagram of a parallel computer according to an embodiment of the present invention;
FIG. 3 is a sequence diagram of the synchronization process according to the embodiment; and
FIG. 4 is a schematic for explaining an application example of the embodiment.