Claims
- 1. A network comprising:
a master; a slave in communication with the master, the slave including
(n) input terminals adapted to receive a (n)-bit input, wherein (n) represents an integer greater than one, and (n) output terminals adapted to communicate a (n)-bit output; and a processor and memory electrically connected to the (n) input and (n) output terminals, the memory being configurable to include a block consisting of 2(n) sub-blocks, each sub-block having (n) bits.
- 2. A network as set forth in claim 1 wherein the slave further includes (m) control terminals electrically connected to the processor and memory, and wherein the memory is configurable to include 2(m) blocks, each block consisting of 2(n) sub-blocks, each sub-block consisting of (n) bits.
- 3. A network as set forth in claim 2 wherein (n) is equal to four and (m) is equal to two.
- 4. A network as set forth in claim 3 wherein the slave further includes an (m+1) control terminal electrically connected to the processor and memory.
- 5. A network as set forth in claim 1 wherein the network further comprises a bus, and wherein the master and slave communicate via the bus.
- 6. A network as set forth in claim 5 wherein the bus consists of up to (n) wires.
- 7. A network as set forth in claim 5 wherein the bus consists of two wires.
- 8. A network as set forth in claim 5 wherein the master further includes a low-voltage power source, and wherein the bus also transmits low-voltage power to the slave.
- 9. A network as set forth in claim 5 wherein the bus is an AS-Interface cable, and wherein the master and slave are compatible with the AS-Interface cable.
- 10. A network as set forth in claim 1 wherein the processor is selected from the group consisting of a microprocessor, a PLC, a microcontroller, and an ASIC.
- 11. A network comprising:
an AS-Interface compatible master; an AS-Interface cable; an AS-Interface compatible slave in communication with the AS-Interface master via the AS-Interface cable, the AS-Interface slave including
four input terminals adapted to receive a four-bit input; four output terminals adapted to communicate a four-bit output; two control terminals adapted to communicate a two-bit control; and a microprocessor and memory electrically connected to the input, output, and control terminals, the memory being configurable to include four blocks, each block consisting of 16 sub-blocks, and each sub-block consisting of four bits.
- 12. A method of communicating data over a network, the network comprising
a master, a slave in communication with the master, the slave including one or more terminals adapted to communicate (n)-bit messages, where (n) is an integer greater than one, and a processor and memory electrically connected to the terminals, the memory being configurable to include a block consisting of 2(n) sub-blocks, each sub-block having (n) bits, the method comprising the acts of:
communicating a first (n)-bit message from the master to the slave; communicating the first (n)-bit message from the slave to the processor; at the processor and memory,
identifying one of the sub-blocks with the first (n)-bit message; obtaining the identified sub-block; communicating a second (n)-bit message including the obtained data from the processor to the slave; and communicating the second (n)-bit message from the slave to the master.
- 13. A method as set forth in claim 12 wherein the one or more terminals include (n)-input terminals adapted to receive an (n)-bit message and (n)-output terminals adapted to output an (n)-bit message, wherein the act of communicating a first (n)-bit message from the slave to the processor includes the act of communicating the first (n)-bit message via the (n)-output terminals, and wherein the act of communicating the second (n)-bit message from the processor to the slave includes the act of communicating the second (n)-bit message via the (n)-input terminals.
- 14. A method as set forth in claim 13 wherein the network further comprises a first (n) channels connecting the (n)-input terminals to the processor and a second (n) channels connecting the (n)-output terminals to the processor, wherein the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the first (n) channels, and wherein the act of communicating the second (n)-bit message via the (n)-input terminals includes communicating each bit of the second (n)-bit message on a respective channel of the second (n) channels.
- 15. A method as set forth in claim 12 wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.
- 16. A method as set forth in claim 12 wherein the network further comprises a two-wire bus, wherein the master and slave communicate via the bus, wherein the act of communicating a first (n)-bit message from the master to the slave includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master to the slave, and wherein the act of communicating the second (n)-bit message from the slave to the master includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the slave to the master.
- 17. A method as set forth in claim 12 wherein the one or more terminals are further adapted to communicate (m)-bit message, where (m) is an integer greater than one, and wherein the memory is configurable to include 2(m) blocks, each block consisting of 2(n) sub-blocks, each sub-block consisting of (n) bits, and wherein the method further comprises the acts of:
communicating an (m)-bit message from the master to the slave; communicating an (m)-bit message from the slave to the processor; at the processor and memory,
identifying one of the blocks with the (m)-bit message; and wherein the act of identifying one of the sub-blocks is performed on the identified block.
- 18. A method as set forth in claim 17 wherein (n) is equal to four and (m) is equal to two.
- 19. A method as set forth in claim 12 and further comprising the acts of:
communicating a third (n)-bit message from the master to the slave; communicating the third (n)-bit message from the slave to the processor; at the processor and memory,
identifying a second sub-block with the third (n)-bit message; obtaining the second identified sub-block; communicating a fourth (n)-bit message including the obtained data of the second identified sub-block from the processor to the slave; communicating the fourth (n)-bit message from the slave to the master; at the master,
storing at least a portion of the second (n)-bit message; and combining the stored portion of the second (n)-bit message with at least a portion of the fourth (n)-bit message.
- 20. A method of communicating data over a network, the network comprising
a master, a slave in communication with the master, the slave including one or more terminals adapted to communicate (n)-bit messages, where (n) is an integer greater than one, and a processor and memory electrically connected to the terminals, the memory being configurable to include a block consisting of 2(n) sub-blocks, each sub-block having (n) bits, the method comprising the acts of:
communicating a first (n)-bit message from the master to the slave; communicating the first (n)-bit message from the slave to the processor; communicating a second (n)-bit message from the master to the slave; communicating the second (n)-bit message from the slave to the processor; at the processor and memory,
identifying one of the sub-blocks with the first (n)-bit message; and writing the second (n)-bit message in the identified sub-block.
- 21. A method as set forth in claim 20 wherein the one or more terminals include (n)-output terminals adapted to output an (n)-bit message, wherein the act of communicating a first (n)-bit message slave from the slave to the processor includes the act of communicating the first (n)-bit message via the (n)-output terminals, and wherein the act of communicating the second (n)-bit message from the slave to the processor includes the act of communicating the second (n)-bit message via the (n)-output terminals.
- 22. A method as set forth in claim 21 wherein the network further comprises (n) channels connecting the (n)-output terminals to the processor, wherein the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the (n) channels, and wherein the act of communicating the second (n)-bit message via the (n)-output terminals includes communicating each bit of the second (n)-bit message on a respective channel of the (n) channels.
- 23. A method as set forth in claim 20 wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.
- 24. A method as set forth in claim 20 wherein the network further comprises a two-wire bus, wherein the master and slave communicate via the bus, wherein the act of communicating a first (n)-bit message from the master to the slave includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master to the slave, and wherein the act of communicating the second (n)-bit message from the master to the slave includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the master to the slave.
- 25. A method as set forth in claim 20 wherein the one or more terminals are further adapted to communicate (m)-bit message, where (m) is an integer greater than one, and wherein the memory is configurable to include 2(m) blocks, each block consisting of 2(n) sub-blocks, each sub-block consisting of (n) bits, and wherein the method further comprises the acts of:
communicating an (m)-bit message from the master to the slave; communicating an (m)-bit message from the slave to the processor; at the processor and memory,
identifying one of the blocks with the (m)-bit message; and wherein the act of identifying one of the sub-blocks is performed on the identified block.
- 26. A method as set forth in claim 25 wherein (n) is equal to four and (m) is equal to two.
- 27. A method as set forth in claim 20 and further comprising the acts of:
providing a (p)-bit message, where (p) is an integer greater than (n); decomposing the (p)-bit message to result in the second (n)-bit message and a fourth (n)-bit message, at least part of the second (n)-bit message being a portion of the (p)-bit message and at least part of the fourth (n)-bit message being a portion of the (p)-bit message; communicating a third (n)-bit message from the master to the slave; communicating the third (n)-bit message from the slave to the processor; communicating the fourth (n)-bit message from the master to the slave; communicating the fourth (n)-bit message from the slave to the processor; at the processor and memory,
identifying a second sub-block with the third (n)-bit message; and writing the fourth (n)-bit message in the identified second sub-block.
- 28. A method of communicating data over a network, the network comprising
a master, a bus electrically connected to the master, a slave electrically connected to the bus, the slave including (n) input terminals adapted to received a (n)-bit input, n-output terminals adapted to output a (n)-bit output, (m) control terminals adapted to communicate an (m)-bit control, and an W/R terminal adapted to communicate an W/R control, where (n) and (m) represent an integer greater than one, and a processor and memory electrically connected the input, output, control, and W/R terminals, the memory being configurable to include 2(m) blocks, each block consisting of 2(n) sub-blocks, and each sub block consisting of (n) bits, the method comprising:
setting an W/R control message to a value representing one of a read operation and a write operation; communicating the W/R control message from the master to the slave via the bus; communicating the W/R control message from the slave to the processor via the W/R control terminal; communicating an (m)-bit message from the master to the slave via the bus; communicating the (m)-bit message from the slave to the processor via the (m) control terminals; communicating a first (n)-bit message from the master to the slave via the bus; communicating the first (n)-bit message from the slave to the processor via the (n)-output terminals; at the processor and memory,
identifying one of the blocks with the (m)-bit message; and identifying one of the sub-blocks of the identified block with the first (n)-bit message; if the W/R control message is a value representing a read operation,
obtaining the identified sub-block; communicating a second (n)-bit message including the obtained data from the processor to the slave via the (n)-input terminals; and communicating the second (n)-bit message from the slave to the master via the bus if the W/R control message is a value representing a write operation
communicating a third (n)-bit message from the master to the slave via the bus, communicating the third (n)-bit message from the slave to the processor via the (n) output terminals, writing the third (n)-bit message in the identified sub-block.
- 29. A method as set forth in claim 28 wherein the network further comprises a first (n) channels connecting the (n)-output terminals to the processor, a second (n) channels connecting the (n)-input terminals to the processor, (m) channels connecting the (m) control terminals to the processor, and a W/R channel connecting the W/R terminal to the processor, wherein the act of the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the first (n) channels, wherein the act of communicating the second (n)-bit message via the (n)-input terminals includes communicating each bit of the second (n)-bit message on a respective channel of the second (n) channels, and wherein the act of communicating the third (n)-bit message via the (n)-output terminals includes communicating each bit of the third (n)-bit message on a respective channel of the second (n) channels.
- 30. A method as set forth in claim 28 wherein each block is identified binaryly from (0) to (m−1), and wherein the act of identifying one of the blocks includes identifying the block corresponding to the (m)-bit message, and wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.
- 31. A method as set forth in claim 28 wherein the bus is a two-wire bus, wherein the act of communicating a first (n)-bit message from the master to the slave includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master to the slave, wherein the act of communicating the second (n)-bit message from the slave to the master includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the slave to the master, and wherein the act of communicating the third (n)-bit message from the slave to the master includes the act of sequentially communicating the (n)-bits of the third (n)-bit message from the slave to the master.
- 32. A method as set forth in claim 31 wherein the bus is an AS-Interface cable, and wherein the master and slave are compatible with the AS-Interface cable.
- 33. A method as set forth in claim 28 wherein (n) is equal to four and (m) is equal to two.
- 34. A method as set forth in claim 28 and further comprising the acts of
communicating a fourth (n)-bit message from the master to the slave; communicating the fourth (n)-bit message from the slave to the processor; at the processor and memory, identifying a second sub-block of the identified block with the fourth (n)-bit message; if the W/R control message is a value representing a read operation,
obtaining the second identified sub-block; communicating a fifth (n)-bit message including the obtained data of the second identified sub-block from the processor to the slave via the (n)-input terminals; communicating the fifth (n)-bit message from the slave to the master via the bus; at the master,
storing at least a portion of the second (n)-bit message; and combining the stored portion of the second (n)-bit message with at least a portion of the fifth (n)-bit message; and if the W/R control message is a value representing a write operation,
providing a (p)-bit message, where (p) is an integer greater than (n); decomposing the (p)-bit message to result in the third (n)-bit message and a sixth (n)-bit message, at least part of the third (n)-bit message being a portion of the (p)-bit message and at least part of the sixth (n)-bit message being a portion of the (p)-bit message; communicating the sixth (n)-bit message from the master to the slave via the bus; communicating the sixth (n)-bit message from the slave to the processor via the output terminals; and at the processor and memory, writing the sixth (n)-bit message in the identified second sub-block.
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09/849,900, filed on May 4, 2001, entitled “DISTRIBUTED INTELLIGENCE CONTROL FOR COMMERCIAL REFRIGERATION”; which is a continuation-in-part of International Patent Application No. PCT/US01/08072, filed Mar. 14, 2001, entitled “DISTRIBUTED INTELLIGENCE CONTROL FOR COMMERCIAL REFRIGERATION”; which is a continuation-in-part of U.S. patent application Ser. No. 09/524,938, filed on Mar. 14, 2000, entitled “DISTRIBUTED INTELLIGENCE CONTROL FOR COMMERCIAL REFRIGERATION,” issued as U.S. Pat. No. 6,332,327; all of which are incorporated herein by reference.
Continuation in Parts (3)
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Number |
Date |
Country |
Parent |
09849900 |
May 2001 |
US |
Child |
10461711 |
Jun 2003 |
US |
Parent |
PCT/US01/08072 |
Mar 2001 |
US |
Child |
09849900 |
May 2001 |
US |
Parent |
09524939 |
Mar 2000 |
US |
Child |
PCT/US01/08072 |
Mar 2001 |
US |