Patent Application
20060105802
1. Field of the Invention
The present invention relates generally to a reconfigurable communication system. In particular, the present invention relates to a communication system having a reconfigurable hardware structure to support multiple wireless transmission standards and a reconfiguration method therefor.
2. Description of the Related Art
Conventionally, physical layer design of terminals for communication systems is implemented with Application Specific Integrated Circuits (ASICs) for miniaturization and low-power consumption. Notwithstanding the advantages, however, the ASIC-based implementation has one disadvantage of very low implementation flexibility because once a chip is generated, modification of its internal design is impossible. Another disadvantage is the long design cycle from chip design to chip production.
Recently, wireless transmission standards, such as Code Division Multiple Access 2000 (CDMA2000) and Wideband Code Division Multiple Access (WCDMA), are undergoing rapid evolution. Such evolution is increasing the demand for services that are capable of accessing several wireless transmission standards through one terminal. A terminal capable of supporting wireless transmission standards is required not only to meet the miniaturization and low-power consumption requirements, but also to support multiple wireless transmission standards and to have a shorter design cycle. For example, there is a demand for a terminal supporting both a CDMA2000 1× wireless transmission standard and a WCDMA wireless transmission standard.
As a plan to meet these requirements, a scheme for implementing both of the wireless transmission standards in one chip can be taken into consideration. However, such a scheme increases a chip size due to the inefficient use of computational resources in the chip. Further, when there is a need to add a new wireless transmission standard, the chip must be redesigned. In addition, the long design cycle, which is one problem of the ASIC, results in a long design time in the process of designing a terminal that is capable of supporting multiple wireless transmission standards using the ASIC.
Programmable devices, such as a field programmable gate array (FPGA), a general-purpose processor, and a digital signal processor (DSP), have become alternative plans to meet the short-design cycle requirements. However, the FPGA and the general-purpose processor have the advantage of high implementation flexibility and short design cycle, but have the disadvantage of low computational resource utility and high power consumption, because each are focused on the general purpose application field. The DSP is a device that has high implementation flexibility and is very suitable for the digital signal processing field. However, due to its low operating frequency, the DSP is insufficient to meet all of the requirements of the communication systems that require high computation power.
A great degree of research is being conducted on a structure that is capable of taking into account implementation flexibility of the programmable hardware function, while maintaining the current ASIC's advantage of low power consumption performance. Machines including the reconfigurable hardware are called “configuration computing machines (CCMs)”. Because conventional CCMs lay great emphasis on reconfigurable functions rather than low power consumption, they are not suitable to be applied to a wireless terminal that requires high computational processing capability, miniaturization, and low power consumption.
Accordingly, in order to use reconfigurable hardware for wireless terminals, there is a need to design a structure in which such factors as low power consumption, small hardware size and reconfiguration flexibility are taken into consideration.
It is, therefore, an object of the present invention to substantially solve the above and other problems, and to provide a communication system having a hardware structure that is capable of reconfiguring multiple wireless transmission standards, the system providing implementation flexibility while minimizing a reduction in low power consumption performance, and a reconfiguration method therefor.
According to one aspect of the present invention, a communication system is provided having a reconfigurable hardware structure. The communication system comprises a plurality of processing element (PE) blocks for processing data based on multiple wireless transmission standards, memories for storing data being processed or to be processed by the PE blocks, and a controller for controlling data processing in the PE blocks, a data input operation to the PE blocks and a data output operation from the PE blocks, and controlling transmission of data being processed in and input/output to/from the PE blocks. Each of the PE blocks comprises a plurality of PE modules, and each of the PE modules comprises a predetermined number of PEs that perform different functions, and the operation and input/output of the PE blocks, the PE modules and the PEs are controlled by the controller.
According to another aspect of the present invention, a communication system is provided having a reconfigurable hardware structure. The communication system comprises first and second processing element (PE) blocks for processing data based on multiple wireless transmission standards, an input buffer for storing input data, a first block memory for storing data being processed or to be processed by the first PE block, a second block memory for storing data being processed or to be processed by the second PE block, a transfer memory for storing data transmitted between the first PE block and the second PE block, and a controller for controlling data processing in the first and second PE blocks, a data input operation to the first and second PE blocks and a data output operation from the first and second PE blocks, and controlling transmission of data being processed in and input/output to/from the first and second PE blocks. Each of the first and second PE blocks comprises one or more PE modules, and each of the PE modules comprises a predetermined number of PEs that perform different functions, and operation and input/output of the first and second PE blocks, the PE modules and the PEs are controlled by the controller.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Exemplary embodiments of the present invention will now be described in detail with reference to the annexed drawings. In the drawings, the same or similar elements are denoted by the same reference numerals, even though they are depicted in different drawings. In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for clarity and conciseness.
In the following description, embodiments of the present invention provide a reconfigurable hardware structure providing function implementation flexibility of the general-purpose processors, at the sacrifice of a slight reduction in low power consumption performance which is the advantage of the ASIC. In particular, embodiments of the present invention provide a structure comprised of several heterogeneous processing elements (PEs), taking functions of WCDMA2000 and WCDMA wireless transmission standards into account to minimize a reduction in low power consumption performance. In addition, embodiments of the present invention provide both an arrangement structure of the PEs and an interconnection structure with a memory in order to implement the necessary function using the PEs.
Embodiments of the present invention propose reconfigurable hardware comprised of reconfigurable PEs that perform different functions. The reconfigurable PEs include PEs for supporting CDMA2000 and WCDMA wireless transmission standards, but are not limited thereto. The PEs' operation and all operations related to data transmission are achieved by individual controllers for controlling the operations. Input/output ports and buses for data transmission between PEs, global memories, and interconnections with the PEs are also reconfigurable. The reconfiguration of the reconfigurable hardware is performed according to control signals generated by corresponding controllers. Each controller stores a control sequence in an internal memory, and generates a control signal using a state machine therein. Embodiments of the present invention fix a data bit width taking into account the regularity of data processing, the expediency of efficient compiler design, and the expandability of calculation blocks, and sets the data bit width to 32 bits through an analysis of function blocks supporting the CDMA2000 and WCDMA wireless standards.
Referring to
In an exemplary embodiment of the present invention, there are 4 reconfigurable PEs that perform different functions. The 4 PEs comprise a PEA, a PEB, a PEC and a PED. A predetermined number (for example, 4) of PEs are grouped, to comprise a PE module. For example, 4 PEAs are grouped to comprise a PEA module, 4 PEBs are grouped to comprise a PEB module, 4 PECs are grouped to comprise a PEC module, and 4 PEDs are grouped to comprise a PED module.
The PE modules performing different functions comprise a PE block. An exemplary embodiment of the present invention configures a PEAB block by grouping 4 PEA modules and 1 PEB module and configures a PECD block by grouping 4 PED modules and 1 PEC module, taking an application field into consideration. In order to increase the required number of PEs, the number of PE blocks can be increased. Actually, embodiments of the present invention provide “M” number of PEAB blocks and “N” number of PECD blocks taking into account the expandability during chip implementation. The hierarchical structure of PE, PE modules and PE blocks is subject to hierarchical connection, even in the data transmission connection between PEs. Although PEs in the same PE module are possible for direct connection, data transmission of PEs located in different PE modules is achieved through per-PE module input/output ports. This is to solve the problem that when all PEs have direct connection to each other, extravagant routing line costs for supporting the direct connection must be paid. That is, the hierarchical structure enables the direct connection for the PE connection type within a particular range.
The controller 100 comprises individual controllers for PE blocks, PE modules and PEs. Specifically, the controller 100 can comprise a PEA controller for PEAs, a PEB controller for PEBs, a PEC controller for PECs, a PED controller for PEDs, a PEA module controller for PEA modules, a PEAB block memory controller for shifting data in a PEAB block memory, a PECD block memory controller for shifting data in a PECD block memory, a transfer memory controller for shifting data in a transfer memory, and a local memory bus controller.
Referring to
The input/output of the PEA is expressed with 32 bits. This is because the input/output bits of the PEA include a 5-bit value of the 5-bit register 211, a 5-bit value of the 5-bit counter 213, two 5-bit values calculated by the respective 5-bit logic gates 215 and 216, a 1-bit value of a left 5-bit CLFSR, a 1-bit value of a right 5-bit CLFSR, an output value of the left CLFSR and an output value of the right CLFSR in the order of the least significant bit (LSB) to the most significant bit (MSB). Input/output of each of the PEB, the PEC and the PED is also expressed with 32 bits, and these 32-bit values, compared with that of the PEA, represent result values calculated by their PEs.
Because the PEA includes two left and right operation parts that perform the same operation and have the same structure, only the left operation part PEA-1 will be described for simplicity. Although a description of the right operation part PEA-2 will not be given, it is equal to the description of the left operation part PEA-1.
The 32-bit data input from the input/output ports is loaded into the register 211 and the counter 213. The data loaded into the register 211 and the counter 213 undergoes logic computation by the logic gates 215, and the computation result is provided to the CLFSR0217 and the CLFSR2219. The CLFSR is a reconfigurable LFSR. A count value from the counter 213 may be directly loaded into the CLFSRs 217 and 219 according to a control signal. The CLFSR0217 and the CLFSR2219 are selectively used according to a structure of the LFSR. The CLFSR0217 is used to implement an orthogonal variable spreading factor (OVSF) code (or Walsh code) generator, and the CLFSR2219 is used to implement a WCDMA scrambling code and/or CDMA2000 15-bit pseudo noise (PN) code generator or a long code generator. In order to implement an LFSR having a desired bit length, the CLFSR0217 (or CLFSR2219) can be connected to a CLFSR0 (or CLFSR2) of another PEA. For example, in order to implement a 9-bit Walsh code generator, two CLFSR0s are connected to each other. The connected two CLFSR0s constitute a 10-bit internal register, and only 9 of the 10 registers are used to implement a 9-bit Walsh code generator.
Referring to
Referring to
Table 1 through Table 3 below show exemplary definitions of each control field and its operation of a PEA with the structures as shown in
Table 1 below shows exemplary definitions of each operation control field and its operation of the PEA. These definitions are applied to each of the PEA-1 and the PEA-2 in the PEA. For a function unit (FU) of the CLFSR0 shown in
For the CLFSR2 shown in
Table 2 below shows exemplary definitions of an input control field and its operation of the PEA. As described above, the PEA comprises two parts that simultaneously perform the same two operations and have the same structure. Inputs Input0 and Input1 to the two individual parts are controlled to be connected to or disconnected from input/output ports of the two parts.
Table 3 shows exemplary definitions of an output control field and its operation of the PEA. Two input/output ports of the PEA are directly connected to two input/output ports MIF0 (module interface 0) and MIF1 (module interface 1) of the PEA module. The PEA input/output ports are controlled to be connected to or disconnected from input/output ports of the PEA module in accordance with Table 3.
Referring to
The PEB has eight input/output ports 0˜7 and two output ports 0˜1. The eight input/output ports comprise two East/West connection ports EW0 and EW1, two South/North connection ports SN0 and SN1, two PEA module ports PEA module0 and PEA module1, and two local memory ports LM0 and LM1. The two output ports comprise two ports to a transfer memory. The PEB can receive inputs from neighboring PEBs, a PEA module, or a local memory. Each of the operation parts PEB-1 and PEB-2 of the PEB is controlled by a PEB controller in the controller 100 shown in
Because the PEB comprises left and right operation parts that perform the same operation and have the same structure, only the left operation part PEB-1 will be described for simplicity. Although a description of the right operation part PEB-2 will not be given, it is equal to the description of the left operation part PEB-1.
Inputs from the neighboring PEBs, the PEA module, and the local memory can be applied to each of inputs IN0, IN1, IN4 and IN5 under the control of the PEB controller. The 3-bit XOR gates XOR0 and XOR1 mainly receive outputs of the PEA, perform an XOR operation on the contents of bits located in a particular position where there are output values of the CLFSR0217 and CLFSR2219 among output values of the PEA, and output the XOR result to the adder/subtractor Adder/Subtractor0. The Adder/Subtractor0 performs addition (or subtraction) on inputs 4 and 5 or outputs from the XOR gates XOR0 and XOR1, and stores the result therein. A correlation value, which is the addition/subtraction result from the Adder/Subtractor0, is output every symbol period. The Shifter0, a shifter for enabling bidirectional bit shifting, performs bit shifting on the output value of the Adder/Subtractor0. An output of the Shifter0 is a 32-bit result value comprising an output of the PEB.
Table 4 through Table 6 below show exemplary definitions of each control field and its operation of a PEB with the structures shown in
Table 4 below shows exemplary definitions of each operation control field and its operation of the PEB. An Adder0 (or Adder1) performs addition or subtraction on a value from a Register0 (or Register1) and an output value of a 3-bit XOR gate XOR0 (or XOR2) or an output value of a 3-bit XOR gate XOR1 (or XOR3) using bit numbers 0˜3. The Register0 (or Register1) initializes with 0, loads a new value input to the input/output port, or keeps the current value using bit numbers 4, 5, 6 and 7. A Shifter0 (or Shifter1), which is a shifter for performing bit shifting, can perform bit-by-bit shifting from the left 15 bits to the right 16 bits using bit numbers 8˜12 and 13˜17.
Table 5 below shows exemplary definitions of an input control field and its operation of the PEB. Each control value allocates eight input/output ports 0˜7 to each of ten inputs IN0˜IN9. That is, each of the ten inputs is connected to one of the eight input/output ports. Each of the eight input/output ports connects with a PEB neighboring in the East/West direction through two ports EW0 and EW1, connects with a PEB neighboring in the South/North direction through two ports SN0 and SN1, connects with two PEA module's input/output ports PEA Module 0 and PEA Module 1 of a PEA module connected to the corresponding PEB, and connects with a local memory of a PEAB block including the corresponding PEB through two ports LM0 and LM1.
Table 6 below shows exemplary definitions of an output control field and its operation of each PEB. Each of outputs Output0 and Output1 of the PEB includes outputs passing through eight input/output ports 0˜7 and outputs passing through two output ports 0˜1. Because the eight input/output ports and the two output ports remain in a Z (that is, high impedance) state when there is no output for Output0 (or Output1) of the PEB, only the ports having an output are enabled.
Referring to
Input0 and input1 are inputs from a local memory, internal registers, a neighboring PEC, and neighboring PECD blocks. The Input0 and input1 selected by the multiplexers MUX_A and MUX_B are delivered to the Register A and the Register B, respectively. An output of the Register A is delivered to inputs of the 16-bit multiplier, the MUX_shift and the MUX_add_A, the 32-bit adder, the 1's population counter/bit reverser, and the Register C. An output of the Register B is delivered to inputs of the 16-bit multiplier, and the MUX_add_B and the MUX_sel. The 16-bit multiplier performs multiplication on outputs of the Register A and the Register B. An output of the 16-bit multiplier is provided to an input of the 32-bit adder via the MUX_add_A, and is also provided to an input of the 32-bit shifter via the MUX_Shift. The 32-bit adder selects two outputs from among an output of the Register A and an output of the 16-bit multiplier, both passing through the MUX_add_A, and an output of the Register B and an output of the Register C, both passing through the MUX_add_B, and performs addition on the selected outputs. An output of the 32-bit adder is provided to the 32-bit shifter, the condition checker, and the state register via the MUX_Shift.
The 1's population counter/bit reverser performs as a counter that counts the number of 1s in a value of the Register A, also performs as a bit reverser for bit-reversing the value of the Register A. The operation of the 1's population counter/bit reverser is controlled according to a control value of the PEC controller. The 1's population counter/bit reverser provides the count or bit-reversing value to the 32-bit shifter via the MUX_Shift. The condition checker controls the MUX_sel such that one of the value of the Register A and the value of the Register B is provided to the Register C according to conditions of the output of the 32-bit adder, that is the output SR of the state register and the control value of the PEC controller (not shown).
The register file, which are a group of registers for temporarily storing data, is comprised of four registers TR0˜TR3. Each of the registers TR0˜TR3 can store one of an output value of the MUX_Acc, values MEMa and MEMb read from the local memory, and a value stored therein. The MUX_OUT1 outputs one of the output values of the Register A, the Register B and the register file. The MUX_OUT0 outputs one of the output values of the Register C and the MUX_Acc. Outputs OUT0 and OUT1 of the MUX_OUT0 and MUX_OUT1, which are two possible output results of the PEC, are 32-bit calculation result values.
Operations and their input/output-related control of the 16-bit multiplier, the 32-bit adder, the 32-bit shifter, the condition checker, the 1's population counter/bit reverser, the state register, the register file TR0˜TR3, and remaining registers and multiplexers, are controlled by the PEC controller (not shown) in the controller 100 shown in
Referring to
The PED comprises a 32-bit logic operator, a 32-bit adder, a 32-bit shifter, a condition checker, a 1's population counter/bit reverser, a state register, a register file TR0˜TR3, and remaining registers and multiplexers (MUXs). Input0 and Input1 are inputs from a local memory, internal registers, a neighboring PED, and neighboring PECD blocks. The Input0 and input1 selected by the multiplexers MUX_A and MUX_B are delivered to the Register A and the Register B, respectively. An output of the Register A is delivered to inputs of the 32-bit adder, the 32-bit logic operator, the 1's population counter/bit reverser, the 32-bit shifter through the MUX-Shift and the Register C through the MUX_sel and the MUX_Acc. An output of the Register B is delivered to inputs of the 32-bit adder, the 32-bit logic operator, and the Register C through the MUX_sel and the MUX_Acc. The 32-bit adder performs addition on outputs of the Register A and the Register B. An output of the 32-bit adder is provided to the 32-bit shifter via the MUX_Shift. The 32-bit logic operator performs a logic operation on the outputs of the Register A and the Register B. The operation result of the 32-bit logic operator is provided to the 32-bit shifter, the condition checker and the state register D via the MUX_Shift.
The 1's population counter/bit reverser counts the number of Is in a value of the Register A, and provides the count value to the 32-bit shifter via the MUX_Shift. The 1's population counter/bit reverser also performs as a bit reverser. The condition checker controls the MUX_sel such that one of the value of the Register A and the value of the Register B is provided to the Register C according to conditions of the output of the 32-bit adder, that is the output SR of the state register and the control value of the PED controller (not shown). The register file, a group of registers for temporarily storing data, is comprised of four registers TR0˜TR3. Each of the registers TR0˜TR3 can store one of an output value of the MUX_Acc, values MEMa and MEMb read from the local memory, and a value stored therein. The MUX_OUT1 outputs one of the output values of the Register A, the Register B and the register file. The MUX_OUT0 outputs one of the output values of the Register C and the MUX_Acc. Outputs OUT0 and OUT1 of the MUX_OUT0 and MUX_OUT1, which are two possible output results of the PED, are 32-bit calculation result values.
Operations and their input/output-related control of the 32-bit adder, the 32-bit logic operator, the 32-bit shifter, the condition checker, the 1's population counter/bit reverser, the state registers, the register file TR0˜TR3, and remaining registers and multiplexers are controlled by the PED controller (not shown) in the controller 100 shown in
Referring to
One PEA module can implement a CLFSR of a maximum of 20 bits by connecting 5-bit CLFSRs of its individual PEAs. The PEA module has two input/output ports 0˜1. Because the input/output ports are connected to input/output ports of PEAs in the PEA module and are externally connected to the PEB, data transmission/reception between the PEA and the PEB is performed by this connection (see
Table 9 below shows exemplary definitions of an input/output control field and its operation of a PEA module having the structure shown in
In Table 9, IDLE indicates that there is no input/output from the PEA, OUT_PEB indicates activation of an operation of transmitting outputs from input/output ports of the PEA to the PEB connected to the PEA, and IN_PEB indicates activation of an input from the PEB to the PEA's input/output ports. In addition, OUT_LM indicates activation of an operation of transmitting outputs from the input/output ports of the PEA to a corresponding local memory, and IN_LM indicates activation of an input from a corresponding local memory to the PEA's input/output ports.
Referring to
Referring to
Referring to
Referring to
In the process of performing access to the local memory and the transfer memory, an enable/address control signal is generated by a controller corresponding to the PEA modules and PEB for performing the access. The local memory serves as a buffer for external-outputting the PEAB block data and inputting external data to the PEAB block. An input/output interface has two READ ports and two WRITE ports, and an enabling/addressing control operation related to reading/writing is achieved by a controller for the devices (that is, PEA module, each PEB, and transfer memory) for accessing the local memory. A stored data width of the memory also has a 32-bit width like the data width.
Referring to
In the process of performing an access to the local memory and the transfer memory, an enable/address control signal is generated by a controller corresponding to the PECs and PEDs for performing the access. A PEC0, a PEC1, a PEC2 and a PEC3 have bidirectional connections to PED Module0, PED Module1, PED Module2, and PED Module3, respectively. The local memory serves as a buffer for external-outputting of the PECD block data and inputting external data to the PECD block. An input/output interface has two READ ports and two WRITE ports, and an enabling/addressing control operation related to reading/writing is achieved by a controller for the devices (that is, each PEC, each PED, and transfer memory) for accessing the local memory. While the PEAB block's local memories are accessible only in the PEA module, the PECD block's local memories are accessible in each PED. A stored data width of the memory also has a 32-bit width like the data width.
Referring to
The PEAB block memory 320, the PECD block memory 330 and the transfer memory 340 comprise a global memory. The PECD block memory 330 has “L” memory channels, and each channel's memory comprises two memory banks. Each memory bank has two READ/WRITE ports. The global memory comprised of the three memories 320, 330 and 340 has its associated controller, and the controller generates an enable signal and read/write address signals for the read/write operation of the global memory. A PECD block memory controller generates the enable signal and the address signal, and also generates a signal used for selecting a memory channel and a memory bank of the PECD block memory 330.
The PEAB block memory 320 is used for data transmission with M PEAB block's local memories 350, and is controlled by the PEAB block memory controller. Table 10 below shows exemplary control information and control signals generated by the PEAB block memory controller.
Enable signals and address signals are used for a read/write operation from/into the memory. Two enable signals en_csm_r0,r1,w0,w1 for each reading/writing are used for enabling the PEAB block memory 320, and 2*N enable signals en_ab_r0,r1,w0,w1 for each reading/writing are used for enabling the M PEAB block's local memories 350. In addition, address signals addr_csm_r0,r1,w0,w1 for the PEAB block memory 320, for indicating a corresponding memory position, and address signals addr_ab_r0,r1,w0,w1 for the M PEAB block's local memories 350, are used to perform the read/write operation.
The transfer memory 340 is used for data transmission with the M PEAB block's local memories 350 and the N PECD block's local memories 360, and is controlled by the transfer memory controller. Table 11 below shows exemplary control information and control signals generated by the transfer memory controller. Two enable signals en_tfm_r0,r1,w0,w1 for each reading/writing are used for enabling the transfer memory 340, 2*M enable signals en_ab_r0,r1[M] for enabling the M PEAB block's local memories 350 are used for performing the read operation, and 2*N enable signals en_cd_w0,w1[N] for enabling the N PECD block's local memories 360 are used for performing the write operation. In addition, address signals addr_tfm_r0,r1,w0,w1 for the transfer memory 340, for indicating a corresponding memory position, are used for performing reading/writing, address signals addr_ab_r0,r1[M] for the M PEAB block's local memories 350 are used for the read function, and address signals addr_cd_w0,w1[N] for the N PECD block's local memories 360 are used for the write function.
The PECD block memory 330 is comprised of 2*L memory banks and is used for data transmission with the N PECD local memories 360, and its channel bank selection operation and enabling/addressing operation are controlled by the PECD block memory controller. Table 12 below shows exemplary control information and control signals generated by the PECD block memory controller. Enable signals and address signals are used for a read/write operation from/into the memory. Two enable signals en_rvm_r0,r1,w0,w1 for each reading/writing are used for enabling the PECD block memory 330, and 2*N enable signals en_cd_r0,r1,w0,w1 for each reading/writing are used for enabling the N PECD block's local memories 360. In addition, address signals addr_rvm_r0,r1,w0,w1 for the PECD block memory 330, for indicating a corresponding memory position, and address signals addr_cd_r0,r1,w0,w1[N] for the N PECD block's local memories 360, are used to perform the read/write operation. Further, channel selection signals sel_ch_r,w and bank selection signals sel_bank_r,w are provided for selecting memory channel and bank.
Referring to
There are four local memory buses provided in the PEAB Bus for data transmission between PEAB blocks, and there are four local memory buses provided in the PECD Bus for data transmission between PECD blocks. The local memory buses are controlled by a local memory bus controller. Control signals include bus selection signals, enable signals and read/write address signals, used by a local memory to access the local memory buses. The bus selection signals are used for selecting one of the four PEAB bus lines used by the local memory buses for data reading/writing, and the enable signals are used for enabling the selected bus. The address signals indicate a data read/write position in the corresponding PEAB block or PECD block's local memories.
The input buffer 310 is connected to the PEAB Bus, and its output is controlled by the local memory bus controller. Table 13 below shows exemplary control information and control signals generated by the local memory bus controller. The following bus selection signals are provided, including sel_bus_ab_w0,w1,r0,r1[M] and sel_bus_cd_w0,w1,r0,r1[N] for selecting the PEAB Bus and the PECD Bus, enable signals en_ab_w0,w1,r0,r1[M] and en_cd_w0,w1,r0,r1[N] for enabling the PEAB Bus and the PECD Bus, and address signals addr_ab_w0,w1,r0,r1[M] and addr_cd_w0,w1,r0,r1[N] for indicating data storage positions in the M PEAB block's local memories 350 and the N PECD block's local memories 360.
The input buffer 310 is a data inputting/storing space having two input ports and two output ports. The individual input ports are used for receiving input data on an I arm and a Q arm, respectively. The input buffer stores input data from the external hardware, and transmits the input data to the PEAB block's local memories.
As can be understood from the foregoing description, embodiments of the present invention provide a reconfigurable hardware structure in which multiple wireless transmission standards are taken into consideration, thereby making it possible to modify the existing function and add new functions through hardware reconfiguration. In addition, embodiments of the present invention provide higher implementation flexibility in adding a new wireless transmission standard.
While the present invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 60/622,788 entitled “Reconfigurable Hardware Structure Supporting Multiple Wireless Transmission Standards” filed in the United States Patent and Trademark Office on Oct. 29, 2004, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60622788 | Oct 2004 | US |
