For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings in which:
a is a CP-SC data block structure in a transmitter according to an embodiment of the invention;
b is a CP-SC data block structure in a receiver according to an embodiment of the invention;
Reference will now be made to
After the data is encoded and modulated, the data is input into the Add CP block 30. The data may be encoded by any type of channel encoder (not shown) and the signal may be modulated by any modulation alphabet, e.g. PSK, QAM. The Add CP block 30 appends a cyclic prefix (CP) to each data block. The CP is actually a copy of the last portion of the data block. The length of the CP is greater than the maximum delay spread. The signal is then up-converted and transmitted.
An example of the data block structure with the CP added is shown in
Returning to
The equalized signal is then transformed back into a time domain signal by the IFFT block 40. The time-domain received signal with the CP removed in a CP-SC system can be expressed as:
y=Hx+n (1)
where y, x and n are the M size received signal vector, the transmitted signal vector and the noise vector in each data block of size M, respectively. H is the time varying cyclic convolution channel matrix such as,
where the element hij implies for the channel response of j-th path at i-th symbol period, L is the number of paths and M is the size of the data block.
When the channel varies slowly and remains quasi static during the same data block, H can be approximately seen as a constant cyclic convolution matrix so which gives:
H=Ω*ΛΩ (3)
where Λ is a diagonal matrix and Ω is an M-size FFT matrix.
Returning to
M/(M+L) (4)
However in a fast fading channel, especially one which varies within the same data block, equation 3 cannot be modelled as an approximate solution for channel matrix H. This results in significant performance degradation with one tap FDE.
One solution is to reduce the length of the block size. However as discussed in relation to Type III algorithms, this reduces the bandwidth efficiency since the length of the CP is not reduced. This is shown in
M/(2L+M) (5)
An embodiment of the invention will now be described showing a CP SC system for high Doppler which has the same bandwidth efficiency as the conventional system.
In accordance with an embodiment of the present invention, a higher modulated CP is proposed to shorten the data block length.
Reference is now made to
a shows the data block at different stages of processing in the transmitter.
As shown in
x=[x1x2 . . . x2M]T (6)
where xn represents a data bit and superscript T represents transposing.
According to an embodiment of the present invention the original data block is divided into parts. Each part is input into a different modulator, one modulator being a higher order modulator than the other modulator. The higher modulated part is used as the CP.
According to one embodiment of the invention, at the transceiver, data block Da 60 is input into a serial to parallel converter block 92. The 2M bits of data block 60 are then separated into two parts; a first part 62 of length 2M−4L and a second part 64 of length 4 L.
The first part 62 is modulated by a first modulation scheme. In
In accordance with an embodiment of the invention the modulation scheme applied to the first part 62 of the data block divides the data block into a plurality of sub blocks. In a further embodiment of the invention the applied modulation scheme reduces the length of the first part of the data block.
In a further embodiment of the invention, in the case where the Doppler is very high, the first part 62 of the data block can be broken into more than two sub-blocks. The number of sub blocks the data block is broken into is dependent on the type of modulation scheme used. For example the data block may be broken into four sub-blocks, in this case 64QAM modulation is needed.
The second part 64 of the data block is defined as:
[x2M−4L+1x2M−4L+2 . . . x2M]T
The second part 64 of the data block is input into a higher order combination (HMC) modulator.
According to an embodiment of the invention the second part 64 is input into 16QAM modulator 102. Applying a 16QAM modulation to the 4L bits, results in a block 70 of length L.
Block 70 of length L is then copied. In one embodiment of the invention block 70 may be stored temporarily in a memory 105 in the transmitter 90 before block 70 is combined with the remaining part of the data block.
The two copies of the higher order modulated block 70 of length L are then appended to the ends of blocks Da172 and Da274 at combiner 104 to form a combined data block 76 of length M as shown in
As can be see seen from
M/(M+L) (7)
This is the same as the efficiency of the conventional system given in equation (4). However, since each data block is length M/2 the system is more robust to high Doppler.
In further embodiments of the present invention the data block can be split into 4 or 8 sub-blocks thereby increasing the systems resistance to high Doppler. A higher-order modulation must then be applied to maintain the same spectrum efficiency.
b shows how the received data block is processed when it is received in the receiver 91. Reference will also be made to
In accordance with an embodiment of the invention the receiver 91 is arranged to divide the composite data block into the same number of sub blocks that resulted from the modulation of the first part 62 of the data block in the transmitter.
According to one embodiment of the invention the type of modulation is predefined and the receiver has knowledge of the type of modulation used in the receiver.
According to another embodiment of the invention modulation information may be transmitted from the transmitter to the receiver.
When the signal is received at the receiver 91, the Remove CP block 93 removes the CP. The received signal block is then divided into two sub blocks 78 and 79.
After dividing the received signal block into two sub blocks 78 and 79, the sub-blocks are processed separately in two paths of the receiver arranged in parallel. The first path for equalising the sub block 78 contains an M/2 sized FFT block 94a, FDE block 95a and IFFT block 96a. The second path for equalising the second sub block 79 contains an M/2 sized FFT block 94b, FDE block 95b and IFFT block 96b.
In one embodiment of the invention the number of processing paths provided in the receiver is dependent on the number of sub blocks that the composite data block is divided into.
Sub block 78′ output from the IFFT block 96a contains the first sub block Da 172 together with block 70 of length L. Sub block 79′ output from the IFFT block contains the second sub block Da 274 together with another copy of block 70.
According to an embodiment of the invention, since the receiver is aware of the type of modulation used in the transmitter, the receiver has knowledge of the length of each sub block. After the receiver synchronises the received frames the data in each sub block can be determined by the length of the data.
The higher modulated block 70 of length L is then removed from each of the sub blocks and combined in combiner 97 before being input into 16QAM de-mapping block 98 to be demodulated. Meanwhile, the first and second sub blocks 78 and 79 are input into a 4QAM de-mapping block 99 to be demodulated.
The output of the two modulators is then combined and input into a parallel to serial block 100, resulting in data block Da of length 2M.
In alternative embodiments of the invention there may be a different number of modulators and equaliser paths in the receiver. It should be appreciated that the number of modulators and equaliser paths in the receiver is dependent on the number of sub blocks.
Due to the higher order modulation, the Energy per bit per noise power spectral density (EbNo), which defines Spectral Noise Density (SNR) per bit, will decrease. This loss is compensated for in the receiver which combines the repeated high order modulation blocks L in combiner 97. For example, the equal gain combining (EGC) can be utilized in the combiner to compensate the EbNo loss. Alternatively other combining schemes such as maximum ratio combining (MRC) can be also be applied in combiner 97.
In step S1 the first part of the information is modulated according to a first modulation scheme to provide a first data block.
In step S2 the second part of the information is modulated according to a different modulation scheme to provide a second data block.
In step S3 the first data block is appended to the second data block to form a composite data block.
In step S4 the composite data block is transmitted.
Comparative results. Table 1 below compares the complexity of the conventional scheme and a scheme in accordance with the present invention.
It is therefore shown that the implementation complexity could be reduced by around 11% by the embodiment of the invention in the case of M as 512.
As previously discussed, the bandwidth efficiency of the described embodiment of the invention with HMC is the same as that of the conventional system without shortening the data block. In the case of M as 512 and L as 16 the bandwidth efficiencies according to equations (4), (5) and (7) are 96.96%, 94.11% and 96.96% respectively
The required data processing functions in the above described embodiments of the present invention may be implemented by either hardware or software. All required processing may be provided in a centralised controller, or control functions may be separated. Appropriately adapted computer program code products may be used for implementing the embodiments, when loaded to a computer, for example for computations required when combining the sub blocks to form a composite block. The program code product for providing the operation may be stored on and provided by means of a carrier medium such as a carrier disc, card or tape. Implementation may be provided with appropriate software in a control node.
The present invention is described in the general context of method steps, which may be implemented in one embodiment by a program product including computer-executable instructions, such as program code, executed by processor and computers in networked environments. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps.
Software and web implementations of the present invention could be accomplished with standard programming techniques with rule based logic and other logic to accomplish the various database searching steps, correlation steps, comparison steps and decision steps. It should also be noted that the words “component” and “module,” as used herein and in the claims, is intended to encompass implementations using one or more lines of software code, and/or hardware implementations, and/or equipment for receiving manual inputs.
The applicant draws attention to the fact that the present invention may include any feature or combination of features disclosed herein either implicitly or explicitly or any generalisation thereof, without limitation to the scope of any of the present claims. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
Number | Date | Country | Kind |
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0615201.1 | Jul 2006 | GB | national |