This invention relates to the field of integrated circuits. More particularly, this invention relates to the field of integrated circuits comprising an array of interconnected programmable logic elements (e.g field programmable gate array integrated circuits) and the communication mechanisms within such integrated circuits.
It is known to provide integrated circuits comprising an array, or other regular structure, of interconnected programmable logic elements. Field programmable gate array integrated circuits are one example of this type of integrated circuit. These integrated circuits are useful for a variety of different purposes. One example use is for emulating an integrated circuit design before that integrated circuit design is manufactured. Another use is providing an integrated circuit with a desired functionality without having to manufacture a specific integrated circuit to provide that functionality.
One way of using such arrays of interconnected programmable logic elements is to use them to implement significant functional circuitry blocks known as macrocells (in the sense of system-on-chip (SOC) designs. Such macrocells typically correspond to functional units such as a processor core, a memory controller, a DSP engine, or other major portions of a typical system-on-chip integrated circuit design. These macrocells may be designed and provided by the same company, or from a collection of different companies. This design style in which a significant proportion of the design consists of macrocells connected using shared communication channels, such as buses or networks, will be recognised as SOC design. When the macrocells are implemented using the array of interconnected programmable logic elements, they often require a communication mechanism to be established between the macrocells implemented upon the array and between the design implemented upon the array and the circuit elements outside the array.
With the increasing use of macrocells implemented using arrays of interconnected programmable logic elements, and the recognition that such macrocells are often designed to communicate via shared communication channels, it becomes desirable to support such shared communication channels for communication within the array itself
It is known to provide arrays of interconnected programmable logic elements with embedded special purpose hardware, such as multipliers, RAM arrays and the like as these are commonly used.
It is desirable to increase the efficiency with which programmable logic elements within an array of interconnected programmable logic elements are used to provide the required functionality.
Viewed from one aspect the present invention provides an integrated circuit comprising: an array of interconnected programmable logic elements, each logic element performing data processing controlled by a configuration stored after manufacture into said logic element; one or more shared communication channels providing intra-array communication within said array; and a plurality of dedicated communication interface circuits distributed within said array, said dedicated communication interface circuits providing access to said one or more shared communication channels; wherein said logic elements are configured to provide a plurality of functional units, each of said plurality of functional units having an interconnect interface for transferring communication transactions and coupled to one of said plurality of dedicated communication interface circuits; said plurality of dedicated communication interface circuits and said one or more shared communication channels are controlled by said configuration to emulate an interconnect circuit configured to transfer communication transactions between said plurality of functional units via a plurality of interconnect channels; and each of said one or more shared communication channels has a communication bandwidth greater than required to emulate one of said plurality of interconnect channels such that a plurality of interconnect channels share one of said one or more a shared communication channels.
The present invention recognises that the provision of dedicated communication interface circuits distributed within the array of interconnected programmable logic elements itself can provide an overall increase in efficiency as the increasing use of macrocells instantiated within such arrays often requires the use of communication interface circuits to provide access to one or more shared communication channels for intra-array communication. Thus, the area and gates consumed in providing the dedicated communication interface circuits instead of using programmable logic elements to provide this functionality justifies itself given the increased efficiency these provide and the relatively high likelihood of their use in SOC style designs.
Furthermore, the provision of dedicated communication interface circuits and the shared communication channels has the effect that the bandwidth of the dedicated communication mechanisms will typically be higher than the requirements of the functional units which are being provided by the configured logic elements rather than dedicated circuitry. This permits multiple channels of an interconnect circuit of the SOC being emulated to share one of the communication channels provided in a manner which advantageously reduces the communication overhead.
The shared communication channel(s) can be shared in a variety of ways, such as time-division-multiplexing, frequency-division-multiplexing or code-division-multiplexing.
It will be appreciated that the shared communication channels could be formed out of the standard elements of the array, such as the conductors and switch blocks. However, increased efficiency may be achieved when the one or more shared communication channels is also provided in the form of dedicated shared communication channel circuitry. The provision of such dedicated shared communication channel circuitry justifies its inclusion given the efficiency achieved and relatively high likelihood of use.
The shared communication channels could be formed in a variety of different ways, such as a standard bus structure, e.g. an AHB structure as provided by ARM Limited of Cambridge, England. However, an efficient way of interconnecting the logic elements is when the shared communication channel is formed as shared communication channel interconnect circuitry.
The present technique has usefulness when applied purely within the array itself. However, the usefulness of the technique is further enhanced when the one or more shared communication channels also provide communication with circuitry outside the array. The shared communication channel can provide an efficient mechanism for communication with one or more circuit elements outside the array. It will be appreciated that these circuit elements outside of the array may be on the same integrated circuit, or on a different integrated circuit.
It will be appreciated that integrated circuits composed entirely of the array of interconnectable programmable logic elements may be provided and are useful in many circumstances. However, one particular use of the present technique is an integrated circuit which includes both an array of interconnected programmable logic elements and at least one further data processing circuit outside of the array with the one-or-more shared communication channels providing communication between the logic elements within the array and the at least one further data processing circuit. Such a hybrid integrated circuit composed partially of the array of programmable logic elements and partially of dedicated further processing circuitry can provide a good blend of efficiency and flexibility.
It will be appreciated that the at least one further data processing circuit could take a variety of different forms. However, the present technique is well suited to embodiments in which the further data processing circuitry comprises a data processor responsive to a stream of program instructions to perform data processing operations, such as a processor core.
In order to facilitate communication between the array and circuitry outside of the array via the one or more of the shared communication channels, some embodiments may include dedicated bridge circuitry providing a link between the shared communication channel within the array and the circuitry outside of the array.
It will be appreciated that the dedicated communication interface circuits could transfer data between source and destinations in a variety of different ways. However, the present technique is well suited to providing shared communication channels using multi-bit transactions having an associated transaction protocol including control signalling to both the source and destination. Such transactional communication is frequently used within systems employing multiple macrocells and is efficient, flexible and robust.
In order to increase the efficiency of use of the shared communication channels within the array, the array may include arbiter circuitry (either dedicated or formed of programmable logic elements) serving to arbitrate access to the shared communication channels by the plurality of dedicated communication interface circuits within the array.
The routing of communications between the different dedicated communication interface circuits could be controlled in a variety of different ways. However, one efficient technique is to provide each dedicated communication circuit with one or more associated addresses such that a communication transaction is routed across the shared communication channels in dependence upon the destination address associated with that transaction.
While the one or more shared communication channels can have a variety of different forms with differing levels of performance and characteristics, one class of useful implementations is when the one or more shared communication channels completes a data transfer in a time dependent upon at least one of concurrent use of the channel for other data transfers and relative positions within the array of the source and destination. Shared communication channels may be subject to contention and accordingly availability of the channel and transfer times can vary depending upon usage. Furthermore, register stages may be in place along the communication channel which alter the time of transfer depending upon the distance to be covered across the array.
The plurality of dedicated communication interface circuits provided within the array can serve to provide control signals to the logic elements of the array implementing a macrocell with these control signals indicating information such as a dedicated communication channel not being able to accept more data for communication, that data sent for communication was lost and/or that data sent for communication has been received.
The plurality of dedicated communication interface circuits can contain a variety of different circuit elements useful in performing their operation. These circuit elements can include an output buffer for storing data to be transmitted prior to access to the one or more shared communication channels being obtained, and/or an input buffer for storing data received from one or more shared communication channels prior to the data being passed to the logic elements.
The dedicated communication channel interface circuits need not maintain the same communication protocol as is natively used by the macrocells with which they communicate. It may be more efficient if the dedicated communication channel interface circuits transfer data upon the shared communication channels at a number of bits per cycle differing from the number of bits per cycle at which the data is communicated between the logic elements and the dedicated communication channel interface circuits. Thus, the dedicated communication channel interface circuits may, for example, serve to serialise parallel data for communication over the shared communication channels.
In order to facilitate such different communication mechanisms/protocols being employed, a source dedicated communication channel interface circuit may encode data to a different form to the data received from the logic elements with a destination dedicated communication channel interface circuit then performing a complementary decode of that data before passing the data to its logic elements.
The shared communication channels within the array may be a flat shared structure. However, improved efficiency may be achieved when there is a hierarchy of shared communication channels linked by intra-array bridge circuitry.
It is also possible in some embodiments that the array may include a plurality of independent shared communication channels with such communication channels being shared between multiple macroblocks but independent of one another.
It will be appreciated that the shared communication channels can operate in accordance with a variety of different communication protocols and methodology. However, the technique is well suited to embodiments in which the shared communication channels comprise AMBA communication channels as provided by ARM Limited of Cambridge, England.
It will be appreciated that the array of interconnected programmable logic elements could take a variety of different forms. However, the technique is well suited to arrays in the form of a field programmable gate array or a time-multiplexed field programmable gate array.
Viewed from another aspect the present invention provides an integrated circuit comprising: an array of interconnected programmable logic element means for performing data processing controlled by a configuration stored after manufacture into said logic element means; one or more shared communication channel means for providing intra-array communication within said array; and a plurality of dedicated communication interface means distributed within said array for providing access to said one or more shared communication channel means; wherein said logic element means are configured to provide a plurality of functional units, each of said plurality of functional units having an interconnect interface for transferring communication transactions and coupled to one of said plurality of dedicated communication interface means; said plurality of dedicated communication interface means and said one or more shared communication channel means are controlled by said configuration to emulate an interconnect circuit configured to transfer communication transactions between said plurality of functional units via a plurality of interconnect channel means; and each of said one or more shared communication channel means has a communication bandwidth greater than required to emulate one of said plurality of interconnect channels such that a plurality of interconnect channels share one of said one or more a shared communication channel means.
Viewed from a further aspect the invention provides a method of communication within an integrated circuit having an array of interconnected programmable logic elements, each logic element performing data processing controlled by a configuration stored in said logic element, said method comprising the steps: communicating within said array using one or more shared communication channels and a plurality of dedicated communication interface circuits distributed within said array, said dedicated communication interface circuits providing access to said one or more shared communication channels; wherein said logic elements are configured to provide a plurality of functional units, each of said plurality of functional units having an interconnect interface for transferring communication transactions and coupled to one of said plurality of dedicated communication interface circuits; said plurality of dedicated communication interface circuits and said one or more shared communication channels are controlled by said configuration to emulate an interconnect circuit configured to transfer communication transactions between said plurality of functional units via a plurality of interconnect channels; and each of said one or more shared communication channels has a communication bandwidth greater than required to emulate one of said plurality of interconnect channels such that a plurality of interconnect channels share one of said one or more a shared communication channels.
Viewed from a further aspect the present invention provides a method of connecting a plurality of integrated circuit macrocells implemented by an array of interconnected programmable logic elements, said method comprising the steps of:
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
As illustrated in
Implemented within the array 52 are a plurality of different macrocells 54, 56 and 58. Each of these 54, 56, 58 includes a portion of bus interface circuitry 60 implemented using the programmable logic elements within the macrocell 54, 56, 58. This portion of bus interface circuitry 60 communicates with dedicated communication interface circuits 62 which are hardwired rather than being formed from programmable logic elements. These dedicated communication interface circuits 62 connect to dedicated shared communication channel circuitry 38 and communicate via a bridge circuit 44 with further processing circuits 64, 66 and 68 in the form of a processor core 64, a random access memory 66 and input/output circuitry 68. Within the array 52 there is also provided an arbiter circuit 70 which arbitrates access to the local dedicated communication channel 38 by the macrocells 56 and 58. The arbiter circuit 70 may be formed of programmable logic elements or may be a dedicated hardwired arbiter circuitry 70.
The communication channel protocol used within the array 54 may be address based such that each of the dedicated communication interface circuits 62 has one or more associated addresses. A communication transaction being routed on the shared communication channel circuitry 38 has an address indicating its destination sent as part of the transaction and is routed to its destination so as to reach the dedicated communication interface circuit 62 having the matching address allocated thereto. The different macrocells 54, 56 and 58 have different memory address ranges associated therewith and communication transactions within those ranges are routed to the appropriate macrocell 54, 56, 58.
The communication transactions sent via the dedicated shared communication circuitry 38 take a variable amount of time to complete. This time may be dependent upon contention for access to the communication channel, such as is controlled by the arbiter circuit 70. The time to completion may also depend upon the physical distance the transaction has to travel as it may traverse one or more bridge circuits, or one or more buffering registers within the channel, and each of these will introduce a delay, which may in itself be variable. Thus, the data transfers within the array 52 have the character of higher level communication protocols whereby the time taken to complete the transactions can vary as contrasted with a simple data signal sent upon a dedicated conductor which has a fixed time to complete and a fixed timing.
This use of higher level transaction protocols within the array 52 is facilitated by the dedicated communication interface circuit 62 serving to output control signals to the macrocells 54, 56, 58 (composed of logic elements) with which they are associated. These control signals indicate parameters of the communication being provided, such as that the communication channel interface cannot accept more data for communication, data sent was lost, data sent has been received and other communication control signals.
Within such system-on-chip integrated circuits it is normal that the different functional units 78, 80, 82, 84 communicate with one another via an interconnect circuit. Such an interconnect circuit typically provides configurable point-to-point connections as required between the different functional units with appropriate arbitration and control using transmission protocols. Examples of such interconnect circuits are those provided by ARM Limited of Cambridge England utilising the AXI transaction protocol.
While it is possible that the programmable logic elements of the FPGA 74 could be configured to provide the functionality of the interconnect circuit required by the system-on-chip integrated circuit 76, such an approach would be disadvantageously inefficient. As intra-array communication is highly likely to be required when a system-on-chip integrated circuit 76 is implemented using a FPGA 74, a more efficient approach is to provide a plurality of dedicated communication interface circuits 86, 88, 90, 92 distributed throughout the FPGA 74. These dedicated communication interface circuits 86, 88, 90, 92 are in turn coupled to one or more shared communication channels 94 over which communication transactions can be transmitted between the dedicated communication interface circuits 86, 88, 90, 92. The plurality of dedicated communication interface circuits 86, 88, 90, 92 and with the one or more shared communication channels 94 are configured by part of the configuration of the FPGA 74 to emulate an interconnect circuit 96 that would normally be included within the system-on-chip integrated circuit 76. Thus, the designer of the system-on-chip integrated circuit 76 may use a largely similar design to that which would be implemented on an application specific integrated circuit implementation of that system-on-chip integrated circuit 76 and apply this design to a FPGA 74 implemented version of the system-on-chip integrated circuit 76. The different functional units 78, 80, 82, 84 are implemented by suitably configuring the programmable logic elements. The interconnect circuit 96 is provided by suitably configuring the plurality of dedicated communication integrated circuits 86, 88, 90, 92 and the one or more shared communication channels 94.
The dedicated communication interface circuits 86, 88, 90, 92 provide the same interconnect interface to the functional units 78, 80, 82, 84 as would be provided by the interconnect circuit 96 which is being emulated. For example, the dedicated communication interface circuits 86, 88, 90, 92 may present an AXI interface to the functional unit 78, 80, 82, 84 in accordance with the AXI architecture and transaction protocols designed by ARM Limited of Cambridge England.
The present techniques recognised that the use of a plurality of dedicated communication interface circuits 86, 88, 90, 92 and the one or more shared communication channels to emulate the interconnect circuit 96 has the result that the hardware which is forming the emulated interconnect circuit 96 will typically have a higher communication bandwidth than that associated with the rate at which the functional unit 78, 80, 82, 84 can generate or consume communication transactions. The implementation of the functional unit 78, 80, 82, 84 by programmable logic elements configured to provide the same functionality as if those circuit designs had been implemented in dedicated circuitry (e.g. as an application specific integrated circuit) has the consequence that they will typically operate significantly slower. The use of FPGA implementations is nevertheless advantageous in other respects, such as the relative speed with which such implementations may be formed by suitably configuring an already existing general purpose FPGA 74, the relative ease with which such designs may be modified and other practical considerations. However, it is nevertheless true that designs implemented by the programmable logic elements of an FPGA 74 will operate more slowly than the speeds capable of being achieved by dedicated circuitry.
In the context of the design of
It will be appreciated that the sharing of the communication channels 94 can be achieved in a variety of different ways. The sharing may be achieved by time-division-multiplexing, frequency-division-multiplexing, code-division-multiplexing or in some other way. The effect of this multiplexing is that the transactions between the functional units 78, 80, 82, 84 are overlapped with one another on a shared communication channel 94. Thus, before one communication transaction has completed another will already be in progress on the shared communication channel. As an example, if one transaction across the interconnect channel is to transfer a 32-bit data word, then this communication transaction may be divided into the transfer of four 8-bit portions of the full 32-bit data word when it is transferred across the shared communication channel 94. These four 8-bit portions of the 32-bit data word may be interleaved with portions of another communication transaction across another interconnect channel between different functional units 78, 80, 82, 84. This is an example of time-division-multiplexing the shared communication channel between a plurality of interconnect channels being emulated.
Number | Date | Country | Kind |
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0900267.6 | Jan 2009 | GB | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/GB2010/000012 | 1/6/2010 | WO | 00 | 7/7/2011 |