Patent Application
20230345303
The present invention is related to packet transmission, and more particularly, to a communications device and a method for receiving an aggregate packet.
Wi-Fi performs transmission based on contention windows. Rather than completing transmission of multiple packets over multiple operations, it is preferable to combine the multiple packets into one aggregate packet, which allows the multiple packets to be transmitted in a single operation. When an electronic device receives the aggregate packet, it is typical to de-aggregate the aggregate packet by a software driver program to obtain the multiple packets. The driver program is unable to predict a size of the received packet every time, however. It therefore allocates the required register spaces for processing the packets based on a length limit specified in a communications standard. The disadvantage is that memory resources are easily occupied which introduces waste of the memory resources.
Thus, there is a need for a novel architecture and method that can improve usage efficiency of the memory resources without introducing any side effect or in a way that is less likely to introduce side effects.
An objective of the present invention is to provide a communications device and a method for receiving an aggregate packet, to make a driver program of a host device be able to pre-allocate the required buffering spaces based on a shorter packet length.
At least one embodiment of the present invention provides a communications device. The communications device may comprise an aggregate packet de-aggregation device and a transmission interface. The aggregate packet de-aggregation device may be configured to generate multiple subframe packets according to an aggregate packet, wherein a length of each of the multiple subframe packets is less than a length of the aggregate packet. The transmission interface may be configured to couple the communications device to a host device. More particularly, the transmission interface may transmit the multiple subframe packets to the host device, to allow the host device to pre-allocate multiple buffering spaces for receiving the multiple subframe packets according to a maximum allowable length of any of the multiple subframe packets.
At least one embodiment of the present invention provides a method for receiving an aggregate packet. The method may comprise: utilizing an aggregate packet de-aggregation device of a communications device to generate multiple subframe packets according to the aggregate packet, wherein a length of each of the multiple subframe packets is less than a length of the aggregate packet; and utilizing a transmission interface of the communications device to transmit the multiple subframe packets from the communications device to the host device, to allow the host device to pre-allocate multiple buffering spaces for receiving the multiple subframe packets according to a maximum allowable length of any of the multiple subframe packets.
The communications device and the method provided by the embodiments of the present invention can perform de-aggregation on the received aggregate packet in a hardware manner, so that the host device merely needs to satisfy a length requirement of the subframe packets when performing pre-allocation of the buffering spaces. Thus, no matter whether a unit packet having a shorter length such as a medium access control (MAC) service data unit (MSDU) or an aggregate packet having a longer length such as an aggregate MSDU (AMSDU) is received, the present invention can ensure that pre-allocating the buffering spaces based on the length of the unit packet is able to meet the length requirement. It is not necessary to pre-allocate the buffering spaces based on the length of the aggregate packet. Thus, the usage efficiency of the memory resources can be properly improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Wi-Fi packets can be transmitted in medium access control (MAC) service data units (MSDUs) specified by IEEE 802.11 standard. When a transmitter attempts to transmit multiple MSDU packets, the transmitter may aggregate the multiple MSDU packets into one aggregate MSDU (AMSDU) packet, to make the multiple MSDU packets be sent more efficiently under a protocol based on contention windows.
In this embodiment, when the communications device 100 receives an AMSDU packet, the AMSDU de-aggregation engine 110A may generate multiple subframe packets such as multiple MSDU packets according to the AMSDU packet, where a length of each of the multiple MSDU packets is less than a length of the AMSDU packet. The RX packet buffer 120 may register or buffer the multiple MSDU packets output by the AMSDU de-aggregation engine 110A and transmit the multiple MSDU packets to the HCI 130. The HCI 130 may be configured to couple the communications device 100 to the host device 50 (e.g. coupled to the HCI 53 of the host device 50), where the HCI 130 may transmit the multiple MSDU packets to the host device 50, to allow the host device 50 to pre-allocate multiple buffering spaces such as the host buffering list 52L for receiving the multiple MSDU packets according to a maximum allowable length of any of the multiple MSDU packets (e.g. a maximum allowable length specified by the IEEE 802.11 standard). For example, the host device 50 may receive packets (e.g. the multiple MSDU packets) from the communications device 100 based on a condition of pre-allocating the multiple buffering spaces according to the maximum allowable length of the MSDU packet specified by the IEEE 802.11 standard mentioned above, for subsequent processing and usage.
The de-aggregation circuit 112 may perform de-aggregation on the AMSDU packet PAG to generate multiple de-aggregation packets {PdeAG} (e.g. generating a first de-aggregation packet, a second de-aggregation packet and a third de-aggregation packet), where the multiple MSDU packets output from the communications device 100 to the host device 50 (e.g. the MSDU packets generated by the AMSDU de-aggregation engine 110A mentioned above) are generated according to the multiple de-aggregation packets {PdeAG} (e.g. the first de-aggregation packet, the second de-aggregation packet and the third de-aggregation packet), respectively. In addition, each de-aggregation packet of the multiple de-aggregation packets {PdeAG} may have a descriptor configured to carry information of said each de-aggregation packet (e.g. a packet index value, a packet length, a packet type of said each de-aggregation packet and/or information indicating whether this de-aggregation packet has been de-aggregated). Thus, the information of said each de-aggregation packet (e.g. the packet index value and the packet length mentioned above) may indicate whether said each de-aggregation packet is a last de-aggregation packet of the multiple de-aggregation packets {PdeAG} and also indicate the length of said each de-aggregation packet. In some embodiments, the header MAC_header of AMSDU packet PAG may be kept or discarded in one or more of the multiple de-aggregation packets {PdeAG}. In some embodiments, one or more of the padding bytes Padding_1, Padding _2 and Padding _3 of the AMSDU packet PAG of the AMSDU packet PAG may be kept or discarded in one or more of the multiple de-aggregation packets {PdeAG}. In some embodiments, the check code FCS of the AMSDU packet PAG of the AMSDU packet PAG may be kept or discarded in any of the multiple de-aggregation packets {PdeAG}.
For example, the de-aggregation circuit 112 may keep the header MAC_header and the padding byte Padding _1 in the first de-aggregation packet, keep the padding byte Padding_2 in the second de-aggregation packet, and keep the check code FCS in the third de-aggregation packet. Thus, the first de-aggregation packet may be expressed by {RX_Desc_1, MAC_header, AMSDU_subframe_1, Padding_1}, the second de-aggregation packet may be expressed by {RX_Desc_2, AMSDU_subframe_2, Padding_2}, and the third de-aggregation packet may be expressed by {RX_Desc_3, AMSDU_subframe_3, FCS}, where the descriptor RX_Desc_1 may carry information (e.g. a packet index and/or a packet length) of the first de-aggregation packet, the descriptor RX_Desc_2 may carry information (e.g. a packet index and/or a packet length) of the second de-aggregation packet, and the descriptor RX_Desc_3 may carry information (e.g. a packet index and/or a packet length) of the third de-aggregation packet. In another example, for all of the first de-aggregation packet, the second de-aggregation packet and the third de-aggregation packet, the de-aggregation circuit 112 may keep the header MAC_header, and discard the padding bytes Padding_1, Padding_2 and Padding_3 and the check code FCS. Thus, the first de-aggregation packet may be expressed by {RX_Desc_1, MAC_header, Payload_1}, the second de-aggregation packet may be expressed by {RX_Desc_2, MAC_header, Payload_2}, and the third de-aggregation packet may be expressed by {RX_Desc_3, MAC_header, Payload_3}, where Payload_1 is a data payload within the subframe AMSDU_subframe_1, Payload_2 is a data payload within the subframe AMSDU_subframe_2, and Payload_3 is a data payload within the subframe AMSDU_subframe_3. In another example, the de-aggregation circuit 112 may discard the header MAC_header, the padding bytes Padding_1, Padding_2 and Padding_3 and the check code FCS. Thus, the first de-aggregation packet may be expressed by {RX_Desc_1, Payload_1}, the second de-aggregation packet may be expressed by {RX_Desc_2, Payload_2}, and the third de-aggregation packet may be expressed by {RX_Desc_3, Payload_3}.
The header conversion circuit 113 may perform header conversion on the multiple de-aggregation packets {PdeAG} to generate multiple converted packets {PnewHEADER}, respectively (e.g. a first converted packet, a second converted packet and a third converted packet), where each converted packet of the multiple converted packets {PnewHEADER} may have a specific header, to allow the host device 50 to perform subsequent transmission according to a communications standard corresponding to the specific header. For example, an access point (AP) device may comprise the host device 50, and the AP device may further transmit multiple MSDU packets (which are output from the communications device 100 to the host device 50) to other electronic devices according to the communications standard corresponding to the specific header, where the multiple MSDU packets are generated according to the multiple converted packets {PnewHEADER} (e.g. the first converted packet, the second converted packet and the third converted packet).
For example, the header conversion circuit 113 may convert or translate the header MAC_header into a header 802.3_eth_II conforming to IEEE 802.3 Ethernet-II standard. Thus, the first de-aggregation packet may be expressed as {RX_Desc_1, 802.3_eth_II, Payload_1}, the second de-aggregation packet may be expressed as {RX_Desc_2, 802.3_eth_II, Payload_2}, and the third de-aggregation packet may be expressed as {RX_Desc 3, 802.3_eth_II, Payload_3}. In another example, the header conversion circuit 113 may convert or translate the header MAC_header into a header 802.3_SNAP conforming to IEEE 802.3 Sub-network Access Protocol (SNAP) standard. Thus, the first de-aggregation packet may be expressed as {RX_Desc_1, 802.3_SNAP, Payload_1}, the second de-aggregation packet may be expressed as {RX_Desc_2, 802.3_SNAP, Payload_2}, and the third de-aggregation packet may be expressed as {RX_Desc_3, 802.3_SNAP, Payload_3}. In another example, the header conversion circuit 113 may convert or translate the header MAC_header into a header Self_defined conforming to a self-defined standard. Thus, the first de-aggregation packet may be expressed as {RX_Desc_1, Self_defined, Payload_1}, the second de-aggregation packet may be expressed as {RX_Desc_2, Self_defined, Payload_2}, and the third de-aggregation packet may be expressed as {RX_Desc_3, Self_defined, Payload_3}.
If the header conversion circuit 113 is disabled, the payload alignment circuit 114 may obtain the multiple de-aggregation packet {PdeAG} from the de-aggregation circuit 112, and add padding bytes to the multiple de-aggregation packet {PdeAG} to generate multiple aligned packets, respectively, where respective payloads (e.g. the data payloads Payload_1, Payload_2 and Payload_3 mentioned above) of the multiple aligned packets align with one another based on a specific number of bytes: for example, aligning with one another based on 4 byes, aligning with one another based on 8 byes, aligning with one another based on 4 byes, or aligning with one another based on cache line sizes such as 32 bytes, 64 bytes or 128 bytes, in order to improve the efficiency of the host device 50 processing multiple MSDU packets output to the host device 50 from the communications device 100, where the multiple MSDU packets are generated according to the multiple aligned packets. If the header conversion circuit 113 is enabled, the payload alignment circuit 113 may obtain the multiple converted packets {PnewHEADER} from the header conversion circuit 113, and add padding bytes to the multiple converted packets {PnewHEADER} to generate the multiple aligned packets, respectively. It should be noted that
In Step S310, when the AMSDU de-aggregation engine 110A receives a received packet, the flow starts.
In Step S320, the AMSDU de-aggregation packet 110A may determine whether the received packet is a valid AMSDU packet (labeled “Valid AMSDU packet?” in
In Step S330, the AMSDU de-aggregation engine 110A may determine whether a function of performing de-aggregation on the AMSDU packet is enabled (labeled “Enable AMSDU de-aggregation?” in
In Step S340, the AMSDU de-aggregation engine 110A may utilize the de-aggregation circuit 112 to perform de-aggregation on the AMSDU packet to generate multiple de-aggregation packets, and update a receiving descriptor to the multiple de-aggregation packets (labeled “Perform de-aggregation on AMSDU and update RX descriptor” in
In Step S350, the AMSDU de-aggregation engine 110A may determine whether a function of performing header conversion on the multiple de-aggregation packets is enabled (labeled “Enable header conversion?” in
In Step S360, the AMSDU de-aggregation engine 110A may utilize the header conversion circuit 113 to execute header conversion on the multiple de-aggregation packets to generate multiple converted packets (labeled “Execute header conversion” in
In Step S370, the AMSDU de-aggregation engine 110A may determine whether a function of performing payload alignment padding on the multiple de-aggregation packets or the multiple converted packets is enabled (labeled “Enable payload alignment padding?” in
In Step S380, the AMSDU de-aggregation engine 110A may add padding bytes to the multiple de-aggregation packets or the multiple converted packets for data payload alignment (labeled “Add padding bytes for payload alignment” in
In Step S390, the working flow of the AMSDU de-aggregation engine 110A ends, and multiple final MSDU packets may be output to the RX packet buffer 120.
In the embodiment of
For example, the maximum allowable length of one MSDU packet specified in the IEEE 802.11 standard is 2304 bytes, and the maximum allowable length of one AMSDU packet specified in the IEEE 802.11 standard is 7935 bytes. When the host device queues 256 packets in the host buffer 52, 2,031,360 bytes (i.e. 256×7935) of a memory space are required, under a condition where the AMSDU de-aggregation engine 110A is disabled. By comparison, under a condition where the AMSDU de-aggregation engine 110A is enabled, only 589,824 bytes (i.e. 256×2304) of a memory space are required, and the required memory resource can be greatly reduced.
In Step S810, the communications device 100 may utilize an aggregate packet de-aggregation device therein, such as the AMSDU de-aggregation engine 110A shown in
In Step S820, the communications device 100 may utilize a transmission interface therein, such as the HCI 130 shown in
To summarize, the communications device and the method of the present invention can perform de-aggregation on the AMSDU packet by a hardware manner, to ensure that sizes of packets received by the host device are less than or equal to the maximum allowable length of one MSDU packet specified in the IEEE 802.11 standard. Thus, the memory resource can be utilized in a more efficient way.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111114991 | Apr 2022 | TW | national |
