Claims
- 1. A communications system, comprising:
a transmitter for transmitting an angle-modulated signal having communication information and coding information that have been modulated onto a carrier signal at a carrier frequency, said transmitter inserting the coding information into the communication information at regular intervals, said transmitter constructing the angle modulated signal by performing an angle modulation process in which, for each item of the communication information and for each item of coding information, a corresponding phase change in the carrier signal is obtained; and a receiver for receiving the angle-modulated signal; said receiver having a mixer for mixing the angle-modulated signal with a signal having the carrier frequency of the carrier signal such that a baseband signal is obtained in which the carrier frequency has been removed, the baseband signal having a phase profile corresponding to the phase change for each item of the communication information and to the phase change for each item of coding information; said receiver having an analog/digital converter for sampling the phase profile of the baseband signal from the mixer and for converting the baseband signal to a digital data sequence having phase sample values; said receiver having a digital evaluation device that receives the digital data sequence from said analog/digital converter; said digital evaluation device initially separately, obtaining first processing results by processing ones of the phase sample values corresponding to successive items of the communication information and obtaining second processing results by processing ones of the phase sample values corresponding to successive items of the coding information; said digital evaluation device combining the first processing results with the second processing results to obtain a combination result; and said digital evaluation device evaluating the combination result to recover the communication information as a function of the combination result.
- 2. The communications system according to claim 1, wherein said digital evaluation device includes:
a shift register configuration for buffer-storing successive ones of the phase sample values of the digital data sequence from said analog/digital converter; a multiplier for obtaining a first result by multiplying together the ones of the phase sample values that correspond to the successive items of the communication information; a multiplier for obtaining a second result by multiplying together the ones of the phase sample values that correspond to the successive items of the coding information; a combiner for obtaining a combination result by combining the first result and the second result; and a detector device for evaluating the combination result from said combiner to recover the communication information as a function of the combination result.
- 3. The communications system according to claim 2, wherein said combiner is an adder.
- 4. The communications system according to claim 3, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
- 5. The communications system according to claim 2, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
- 6. The communications system according to claim 5, wherein:
the communication information is a sequence and each item in the sequence has a binary value; said transmitter modulates the communication information and modulates the coding information onto the carrier signal such that, in the angle-modulated signal, a phase change of +π/2 in the carrier signal is allocated to a first binary value that will be transmitted and a phase change of −π/2 in the carrier signal is allocated to a second binary value that will be transmitted; and said detector device detects a mathematical sign of the combination result from said combiner to recover the binary value of each item of the sequence of the communication information as a function of the mathematical sign.
- 7. The communications system according to claim 6, wherein a first binary value that results in a phase change of +π/2 in the carrier signal during the angle modulation in said transmitter is chosen as a value for the coding information.
- 8. The communications system according to claim 1, wherein:
a fixed binary value is selected from the group consisting of a zero and a one; said transmitter inserts the fixed binary value as the coding information at regular intervals into the communication information.
- 9. The communications system according to claim 8, wherein a first binary value that results in a phase change of +π/2 in the carrier signal during the angle modulation in said transmitter is chosen as a value for the coding information.
- 10. The communications system according to claim 1, wherein said receiver recovers the communication information by phase-incoherent and single-channel signal processing of the angle-modulated signal, without I/Q splitting the angle-modulated signal.
- 11. The communications system according to claim 1, wherein:
said transmitter inserts the coding information between each two successive items of the communication information; said digital evaluation device of said receiver, initially separately, obtains the first processing result by processing two of the phase sample values corresponding to the successive items of the communication information and obtains the second processing result by processing two of the phase sample values corresponding to the successive items of the coding information.
- 12. The communications system according to claim 11, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
- 13. A receiver unit for receiving angle-modulated signals, comprising:
a receiver for receiving an angle-modulated signal having communication information and coding information, in which the coding information has been inserted at regular intervals into the communication information, and in which the communication information and the coding information have been modulated onto a carrier signal at a carrier frequency using an angle modulation process such that, for each item of the communication information and for each item of the coding information, a corresponding phase change in the carrier signal is obtained; said receiver having a mixer for mixing the angle-modulated signal with a signal having the carrier frequency of the carrier signal such that a baseband signal is obtained in which the carrier frequency has been removed, the baseband signal having a phase profile corresponding to the phase change for each item of the communication information and to the phase change for each item of the coding information; said receiver having an analog/digital converter for sampling the phase profile of the baseband signal from the mixer and for converting the baseband signal to a digital data sequence having phase sample values; said receiver having a digital evaluation device that receives the digital data sequence from said analog/digital converter; said digital evaluation device initially separately, obtaining first processing results by processing ones of the phase sample values corresponding to successive items of the communication information and obtaining second processing results by processing ones of the phase sample values corresponding to successive items of the coding information; said digital evaluation device combining the first processing results with the second processing results to obtain a combination result; and said digital evaluation device evaluating the combination result to recover the communication information as a function of the combination result.
- 14. The receiver unit according to claim 13, wherein said digital evaluation device includes:
a shift register configuration for buffer-storing successive ones of the phase sample values of the digital data sequence from said analog/digital converter; a multiplier for obtaining a first result by multiplying together the ones of the phase sample values that correspond to the successive items of the communication information; a multiplier for obtaining a second result by multiplying together the ones of the phase sample values that correspond to the successive items of the coding information; a combiner for obtaining a combination result by combining the first result and the second result; and a detector device for evaluating the combination result from said combiner to recover the communication information as a function of the combination result.
- 15. The receiver unit according to claim 14, wherein said combiner is an adder.
- 16. The receiver unit according to claim 15, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
- 17. The receiver unit according to claim 14, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
- 18. The receiver unit according to claim 17, wherein:
the communication information is a sequence and each item in the sequence has a binary value; said transmitter modulates the communication information and modulates the coding information onto the carrier signal such that, in the angle-modulated signal, a phase change of +π/2 in the carrier signal is allocated to a first binary value that will be transmitted and a phase change of −π/2 in the carrier signal is allocated to a second binary value that will be transmitted; and said detector device detects a mathematical sign of the combination result from said combiner to recover the binary value of each item of the sequence of the communication information as a function of the mathematical sign.
- 19. The receiver unit according to claim 18, wherein a first binary value that results in a phase change of +π/2 in the carrier signal during the angle modulation in said transmitter is chosen as a value for the coding information.
- 20. The receiver unit according to claim 13, wherein:
a fixed binary value is selected from the group consisting of a zero and a one; said transmitter inserts the fixed binary value as the coding information at regular intervals into the communication information.
- 21. The receiver unit according to claim 20, wherein a first binary value that results in a phase change of +π/2 in the carrier signal during the angle modulation in said transmitter is chosen as a value for the coding information.
- 22. The receiver unit according to claim 13, wherein said receiver recovers the communication information by phase-incoherent and single-channel signal processing of the angle-modulated signal, without I/Q splitting the angle-modulated signal.
- 23. The receiver unit according to claim 13, wherein:
said transmitter inserts the coding information between each two successive items of the communication information; said digital evaluation device of said receiver, initially separately, obtains the first processing result by processing two of the phase sample values corresponding to the successive items of the communication information and obtains the second processing result by processing two of the phase sample values corresponding to the successive items of the coding information.
- 24. The receiver unit according to claim 23, wherein:
said multiplier for obtaining the first result defines a first multiplier; said multiplier for obtaining the second result defines a second multiplier; said shift register configuration sequentially receives the successive ones of the phase sample values of the digital data sequence from said analog/digital converter; said shift register configuration has a first delay element, a second delay element, and a third delay element that are connected in series; at a given instant of time, a fourth given one of the phase sample values is being supplied to said first delay element from said analog/digital converter, a third given one of the phase sample values is stored in said first delay element, a second given one of the phase sample values is stored in said second delay element, and a first given one of the phase sample values is stored in said third delay element; at the given instant of time, said first multiplier multiplies the fourth given one of the phase sample values by the second given one of the phase sample values; and at the given instant of time, said second multiplier multiplies the third given one of the phase sample values by the first given one of the phase sample values.
Priority Claims (1)
Number |
Date |
Country |
Kind |
199 42 944.8 |
Sep 1999 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION:
[0001] This application is a continuation of copending International Application PCT/EP00/08701, filed Sep. 6, 2000, which designated the United States.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/EP00/08701 |
Sep 2000 |
US |
Child |
10094559 |
Mar 2002 |
US |