COMPACT LOW-POWER RECORDING ARCHITECTURE FOR MULTICHANNEL ACQUISITION OF BIOLOGICAL SIGNALS AND METHOD FOR COMPRESSING SAID BIOLOGICAL SIGNAL DATA

Abstract

The present invention relates to a method for compressing signal data of a plurality of biological signals captured by a plurality of implanted measurement devices. The present invention further relates to an implantable sensor configured to carry out said method of compression. The present invention also concerns a method for recovering the plurality of biological signals from the compressed data as well as a system including a plurality of implantable sensors, a transmitter, a receiver and a processor configured to recover the plurality of biological signals from the compressed data.

Description

FIELD OF THE INVENTION

The present invention relates to a method for compressing signal data of a plurality of biological signals captured by a plurality of implanted measurement devices. The present invention further relates to an implantable sensor configured to carry out said method of compression. The present invention also concerns a method for recovering the plurality of biological signals from the compressed data as well as a system including a plurality of implantable sensors, a transmitter, a receiver and a processor configured to recover the plurality of biological signals from the compressed data.

More particularly, the present invention introduces an area- and power-efficient approach for compressive recording of, for example, cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, the present invention concerns a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 μm CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 μW of power within an effective area of 250 μm×250 μm per channel.

BACKGROUND

I. Introduction

Wireless monitoring of brain activity through implantable devices is a promising technology enabling advanced and cost-effective diagnosis and treatment of brain disorders such as stroke, Parkinson's disease, depression and epilepsy [1]-[3]. Recording from multiple sites, however, introduces a major technological bottleneck as the large bandwidth requirement for data telemetry which is not easily achievable by state-of-the-art wireless technology. The increased power consumption of transmission for large recording arrays can cause major safety and biocompatibility concerns regarding the applicability of such devices. Thus, some type of data reduction prior to telemetry is needed to meet the requirements of an implantable device.

Compressive sensing (CS) [4], [5] is an emerging compression method with interesting advantages over traditional methods thanks to its low encoder complexity and universality with respect to the signal model. A compressive sensing system samples a high-dimensional signal into a smaller number of linear measurements than dictated by the Nyquist sampling theorem. CS has been recently studied in the context of biological signals (e.g., ECG [6], [7], EEG [8] and iEEG [9]) to tackle the data rate issue. When compared to thresholding and activity-dependent recording, CS has the advantage of preserving the temporal information and morphology of the signal for the entire recording period. It is also possible to apply CS along with other methods (such as interpacket redundancy removal, Huffman coding [6] or dynamic power management of the front-end LNA (low-noise amplifier)) in order to further relax the stringent energy and bandwidth requirements of implantable system.

While the majority of research presented in literature focus on power minimization of the implantable system, there is also a stringent need to minimize the circuit area in order to include the highest number of recording units into the available die area. Large-scale recording of cortical activity is particularly important in the case of diseases like epilepsy which spread over wide regions of cortical area. Conventional subdural electrodes are used in such applications which consist of several conductive discs mounted in thin plastic and designed to lie on the surface of the cortex. However, the state-of-the-art research targeting such applications progresses toward minimally invasive flexible and dense recording arrays with high-resolution recording capability of intracranial EEG (iEEG) signals [10]-[12]. The high resolution (i.e., small spacing of recording sites) provides the capability of capturing higher frequency activity than traditionally recordable by large widely-spaced electrodes, giving a profound insight into the fundamental mechanisms underlying such abnormalities. Electrocorticographic signals recorded from human cortex can be used as an alternative to invasive spike recordings through penetrating electrodes, in order to control prosthetic limbs in BMIs as shown in [13].

The common microelectronic approach to CS ([8], [14], [15]) consists of on-the-fly compression of consecutive samples of each recording unit over time, either in analog [FIG. 1(a)] or digital [FIG. 1(b)] domain. Even though this approach results in a significant energy efficiency, its large area usage disqualifies the concept for a multichannel recording interface which should include the circuits supporting many channels in a limited die area.

The present invention permits to overcome this issue by providing a new multichannel measurement scheme [see, for example, FIG. 1(c)] along with an appropriate recovery scheme, encoding the whole array into a single compressed data stream. In the proposed approach, the compression is carried out in the analog domain, and in a multichannel fashion. This technique advantageously circumvents the need to place one ADC per channel and results in a significant area saving. Based on this approach, a wireless monitoring system consisting of several recording/compressing units is proposed (FIG. 2). Taking benefit of the area-efficient implementation of CS, the number of recording units implantable, for example, on the cortex which satisfy the energy constraints of the system is scaled up by a factor equal to the compression ratio.

SUMMARY OF THE INVENTION

The present invention relates to a method for compressing a plurality of biological signals provided by a plurality of measurement devices through a plurality of measuring channels, the method comprising the steps of forming a multichannel signal matrix XεR^d×N from the plurality of biological signals where d is a dimension of the biological signal in each channel and in a time-window and N is the number of channels, R meaning a set of real numbers; and obtaining a multichannel measurement vector Y by acquiring M=p/d measurements from each column of the multichannel signal matrix X, to acquire M measurements at each time-window from all channels, where p<<d×N.

The method further includes the step of applying a reshaping operator :R^d×N→R^d·N to the multichannel signal matrix X to transpose said matrix to form a vector of concatenated columns of the multichannel signal matrix X.

The multichannel measurement vector Y is obtained by applying a measurement matrix Φ_MC to the vector of concatenated columns of the multichannel signal matrix X.

The measurement matrix φ_MC is represented in matrix form as follows:

${\Phi }_{\mathrm{MC}}=\left[\begin{array}{ccc}{\Phi }_1& 0\cdots & 0\\ ⋮& \ddots & ⋮\\ 0& \cdots & {\Phi }_d\end{array}\right],{\Phi }_i=\left[\begin{array}{ccc}{\varphi }_i^{1,1}& \cdots & {\varphi }_i^{1,N}\\ ⋮& \ddots & ⋮\\ {\varphi }_i^{M,1}& \cdots & {\varphi }_i^{M,n}\end{array}\right],$

• • where φ_iεR^M×N and φ_i^k,l is uniformly selected from {0,1}.

The multichannel measurement vector Y is determined as follows:

Y=φ _MC (X).

The method further includes the step of recovering a multichannel signal {circumflex over (X)} from the multichannel measurement vector Y using an l_1,2 mixed norm as follows:

$\hat{X}={\Psi }_{\mathrm{MC}}\underset{{\alpha }_{\mathrm{MC}}\in R^{d·N}}{\mathrm{argmin}}||{\alpha }_{\mathrm{MC}}{||}_{1,2}s.t.Y={\Phi }_{\mathrm{MC}}\left({\Psi }_{\mathrm{MC}}{\alpha }_{\mathrm{MC}}\right)$

• • where argmin is argument of the minimum, ∥•∥_1,2 models group sparsity according to the l_1,2 mixed norm, α_MC is a Gabor transform coefficients, is the reshaping operator and ψ_MC is a sparsity matrix.

The method additionally or alternatively includes the step of recovering a multichannel neural signal {circumflex over (X)} from the multichannel measurement vector Y using an l₁ norm as follows:

$\hat{X}=\underset{X\in R^{d\times N}}{\mathrm{argmin}}||{\Psi }_{\mathrm{MC}}^TX_{\mathrm{vec}}{||}_1s.t.Y={\Phi }_{\mathrm{MC}}\left(X\right)$

• • where X_vec is the vector form of X which includes the concatenation of its columns, and the l₁ norm of a vector ξ is defined as ∥ξ∥₁=Σ_i|ξ_i|.

The present invention also relates to an implantable sensor including circuitry configured to carry out the above method.

The present invention further relates to an implantable system including an implantable transmitter and at least one of said implantable sensors, said at least one implantable sensor being connected to the implantable transmitter to communicate the compressed signal to the implantable transmitter for transmission to an external receiver.

The present invention further concerns a system for compressing a plurality of biological signals and recovering biological signals, the system including the previously mentioned implantable system and a receiver for receiving a transmitted compressed signal.

The system further includes a processor configured to receive the compressed signal from the receiver and to process the compressed signal according to the above method to reconstruct the captured biological signals.

The present invention additionally concerns an implantable sensor including a plurality of electrodes for capturing a biological signal, a plurality of amplifiers, each amplifier being connected to a single electrode to amplify the signal captured by each electrode, a random summing circuit for receiving each of the amplified signals, for randomly selecting samples of the amplified captured signals and summing said samples to provide a multichannel measurement signal, and a single analog-to-digital converter for receiving and digitizing the multichannel measurement signal to provide a digital compressed signal.

In the implantable sensor, each amplifier is a low-noise amplifier including a band-pass transfer function.

The implantable sensor further includes a plurality of low-pass filters to limit a high cut-off frequency of the amplified captured signal, each low-pass filter being connected to a single amplifier to receive the amplified captured signal.

The implantable sensor further includes a plurality of additional amplifiers, each additional amplifier being connected to a single low-pass filter to amplify the signal provided by said low-pass filter.

The implantable sensor further includes a plurality of buffered sample-and-hold circuits, each buffered sample-and-hold circuit being connected to a single additional amplifier to receive the signal amplified by said additional amplifier.

The present invention additionally concerns an implantable system including an implantable transmitter and at least one of the above implantable sensors, the least one implantable sensor being connected to the implantable transmitter to communicate the compressed signal to the implantable transmitter for transmission to an external receiver.

The present invention additionally concerns a system for compressing a plurality of biological signals and recovering biological signals, the system including the previously mentioned implantable system and a receiver for receiving a transmitted compressed signal.

Said system further includes a processor configured to receive the compressed signal from the receiver and to process the compressed signal to reconstruct the captured biological signals.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object, features and other advantages of the present invention will be best understood from the following detailed description in conjunction with the accompanying drawings, in which:

FIGS. 1(a), 1(b), and 1(c) illustrate a block diagram of (a) the analog single-channel CS, (b) the digital single-channel CS, and (c) the proposed multichannel CS architectures according to the present invention where d=1024, N=16 and M=4;

FIG. 2 illustrates an exemplary system-level view of the proposed multichannel compressive sensing method used in an implantable neural recording interface [16], where the neural signals sensed at the electrode sites are amplified, randomly projected, summed up and digitized through a single on-chip ADC; an RF unit placed within a burr hole in the skull transmits the compressed and digitized data originating from several recording chips to an external receiver and powers the implanted system;

FIGS. 3(a), 3(b), and 3(c) illustrate the structure of Gabor coefficients of multichannel neural signals in a Gabor window where FIG. 3(a) shows original neural signals: the Gabor coefficients represent group structure along frequencies, FIG. 3 (b) shows the l₁ norm: the Gabor coefficients are scattered and recovery does not respect the group structure and FIG. 3(c) shows the l_1,2 mixed norm: the joint recovery preserves the group structure of Gabor coefficients;

FIGS. 4(a), 4(b), 4(c), and 4(d) illustrate an exemplary circuit implementation of the proposed multichannel CS architecture where FIG. 4(a) shows individual channels, FIG. 4(b) shows a variable-gain summing stage, gain stage and 10-bit SAR ADC (successive-approximation-register analog-to-digital converter) with attenuated binary-weighted DAC (digital-to-analog converter), FIG. 4(c) shows a multi-output random sequence generator, and FIG. 4(d) illustrates a timing diagram of the system;

FIG. 5 consists of FIG. 5(a) that illustrates a compact low-noise differential amplifier and FIG. 5(b) that illustrates a half-circuit equivalent used for noise analysis;

FIG. 6 illustrates an architecture for realizing a high-density recording system where each block of this figure corresponds to one of the implantable chip-electrode combinations of FIG. 2 (excluding the electrodes);

FIG. 7 consists of FIGS. 7(a) and 7(b) that illustrate noise analysis models of the summing stage of FIG. 4 in (a) sampling phase and (b) integrating phase;

FIG. 8 shows a measured frequency response of a stand-alone channel;

FIG. 9 shows a measured input-referred noise of a stand-alone channel;

FIG. 10 consists of FIGS. 10(a) and 10(b). FIG. 10(a) shows a microphotograph of the chip and an individual channel's layout;

FIG. 10(b) shows a power breakdown of a 16-channel compressive sensing array;

FIG. 11 shows one channel of human intracranial EEG recording using strip and greed electrodes implanted on the left temporal lobe, where the recovery SNR is calculated by averaging over 100 blocks of signal in the low-voltage fast activity region;

FIGS. 12(a) and 12(b) shows a comparison of recovery performance using different reconstruction methods for a block of length 1024 and compression ratio of 4, where FIG. 12(a) shows l₁ recovery, SNR_CH1=21.3 dB and FIG. 12(b) shows l_1,2 recovery, SNR_CH1=28.04 dB.

FIG. 13 shows a comparison of mixed norm and sparse recovery performance for different compression ratios where SNRs are averaged over 20 compression blocks;

FIG. 14 illustrates an exemplary neural signal acquisition model, where a 16-channel neural signal is compressed through a 4-measurement compressive acquisition system.

DETAILED DESCRIPTION

II. Theoretical Model

Compressive sensing exploits the known structures in the signals to lower the required sampling ratio below the Nyquist rate, while providing a signal recovery of acceptable quality [17]. The basic concepts of CS are provided in the following discussion, emphasizing the benefit of applying CS in a neural recorder array. A detailed explanation of CS can be found in [4], [5], [18].

A. Compressive Sampling

Compressive signal acquisition prescribes sampling a signal xεR^d with a significantly smaller number of samples than the signal sampled at the Nyquist rate. The linear measurements yεR^m, m<<d are formed by computational projection of the signal onto the measurement matrix φεR^m×d. Compressive measurements over a defined time interval are obtained by

y=φx   (1)

The corresponding block diagram is shown in FIGS. 1(a) and (b). The acquisition system is under-determined, i.e., the number of solutions for x is infinite. However, when the signal is known to be sparse in a basis ψεR^d×d in which x=ψα can be sparsely represented, the sparsest representation of x is the solution to the problem. A signal is said to be sparse in a basis if it can be represented by S non-zero coefficients, i.e., S<<d.

To ensure a successful recovery of x, the linear map φ should satisfy the Restricted Isometry Property (RIP) [19]. The measurement matrix satisfies the RIP for an S-sparse signal x (S non-zero coefficients) and a small restricted isometry constant δ_S<1 if

(1−δ_S)∥x∥₂²≦∥φx∥₂²≦(1+δ_S)∥x∥₂²   (2)

∥x∥₂ represents the l₂ norm of x, which is defined as ∥x∥₂=(Σ_i|x_i|²)^1/2. Sampling matrices with elements generated independently and according to a subgaussian distribution, such as the independent and identically distributed (i.i.d) Gaussian or the Bernoulli/Rademacher distributions (random 0 and 1), satisfy the RIP.

B. Multichannel Acquisition Model of the Present Invention

In the case of multichannel neural recording, measurement limitations such as die area and power consumption suggest the use of a multichannel compression technique rather than acquiring each channel separately. Therefore, it is important to consider a measurement scheme which fulfills the physical constraints of the system. Let XεR^d×N represent the multichannel iEEG signal where d is the dimension of the signal in each channel and in a defined time-window called compression block and N is the number of channels. We define a reshaping operator :R^d×N→R^d·N which transposes the input matrix and vectorizes the resulting matrix by concatenating its columns after each other. The linear compressive measurements are obtained by acquiring M=p/d measurements from columns of X, i.e., M measurement at each time-sample from all channels, where p<<d×N is the total number of measurements. Hence, the multichannel linear map can be represented in matrix form φ_MCεR^(Md)×(dN) as follows:

$\begin{array}{cc}{\Phi }_{\mathrm{MC}}=\left[\begin{array}{ccc}{\Phi }_1& 0\cdots & 0\\ ⋮& \ddots & ⋮\\ 0& \cdots & {\Phi }_d\end{array}\right],{\Phi }_i=\left[\begin{array}{ccc}{\varphi }_i^{1,1}& \cdots & {\varphi }_i^{1,N}\\ ⋮& \ddots & ⋮\\ {\varphi }_i^{M,1}& \cdots & {\varphi }_i^{M,n}\end{array}\right],& \left(3\right)\end{array}$

where φ_iεR^M×N and φ_i^k,l is uniformly selected from {0,1} to approximate a measurement matrix similar to the Bernoulli matrix. The multichannel measurement vector YεR^p is defined as

Y=φ _MC (X)   (4)

C. Sparse Recovery

The recovery of the multichannel iEEG signal from the compressive measurements explicitly employs a multichannel sparsity domain ψ_MC. The underlying neural signals in channels share similar structures. Hence, the transform domain of the multichannel signal is a block-diagonal matrix which presents the sparsity domain of channels along the diagonal and is defined as

ψ_MC=I_Nψ   (5)

ψεR^k×d is the sparsity domain of each channel, I_N is the identity matrix of size N×N, and represents the Kronecker product. The compressive sensing scheme or process [4], [5] attempts to recover the sparsest solution to X from the measurements Y using the following convex minimization:

$\begin{array}{cc}\underset{X\in R^{d\times N}}{\mathrm{argmin}}||{\Psi }_{\mathrm{MC}}^TX_{\mathrm{vec}}{||}_1s.t.Y={\Phi }_{\mathrm{MC}}\left(X\right)& \left(6\right)\end{array}$

where X_vec is the vector form of X which includes the concatenation of its columns. The l₁ norm of a vector ξ is defined as ∥ξ∥₁=Σ_i|ξ_i|. The measurement consistency in the recovery algorithm (Y=φ_MC(X)) pertains to obtaining a signal X which is in accordance with the measurements Y through the measurement matrix φ_MC, i.e., (6) recovers a signal (X) which is sparse in the sparsity domain (ψ_MC) and satisfies the measurement consistency constraint.

D. Mixed Norm Recovery

The multichannel neural signals have high inter-channel dependency, as the signals recorded by the adjacent channels are delayed or scaled version of each other, depending on the spatial resolution and pitch of the electrodes which indicates the propagation of neural activity within the brain. The dependent structure of multichannel neural signals suggests the design of a recovery model that exploits the similarity of neural signals. The Gabor coefficients [20] of iEEG signals recorded by adjacent channels in a Gaussian window are shown in FIG. 3(a). The Gabor coefficients are observed to follow similar activity among neural channels for each frequency.

Sparse recovery induces coefficient-wise sparsity without considering the inter-channel correlation of the neural signals. The neural recovery model should employ the cross correlations of iEEG signals to improve the reconstruction quality. An appropriate model for multichannel neural signals should highlight the group structure of Gabor coefficients, i.e., the model should lead to a sparsity on the number of active frequencies and promote similar activity on the neural channels for the selected frequency.

We model the dependency of neural signals using the l_1,2 mixed norm [21]. The l_1,2 mixed norm of a given vector ξ is defined as

$\begin{array}{cc}||\xi {||}_{1,2}=\sum _g{\left(\sum _m|\xi {|}^2\right)}^{1\text{/}2}& \left(7\right)\end{array}$

where ξ is divided into a set of non-overlapping groups. The elements of ξ are indexed by a pair (g, m), where g defines the group number and m represents the corresponding index inside the group. It is important to differentiate between the l_1,2 mixed norm and the sparsity inducing l₁ norm. In the former, a group of coefficients are discarded or retained together, since the same threshold is applied to the l₂ norm of each group. In the latter, each coefficient is shrunk independently from other elements and the same threshold is applied to each element. Consequently, the l₁ recovery does not model the block structure in the neural signals. However, the l_1,2 norm respects the group structure of neural signals and imposes sparsity on the group of coefficients rather than each coefficient independently. Thus, the l_1,2 scheme results in recovery of dense blocks for sparse number of frequencies. FIG. 3 compares the recovered Gabor coefficients of multichannel neural signal employing sparse and joint recovery in a Gabor window, with the Gabor coefficients of the original neural signal. We observe that the recovered Gabor coefficients using l_1,2 [FIG. 3(c)] yield the same structure as of the original multichannel neural signals [FIG. 3(a)]. Furthermore, the sparse recovery [FIG. 3(b)] does not respect the group structure of neural signals and results in recovery of Gabor coefficients which are sparse and independently spread along different frequencies for each neural channel. This behavior is explained by the fact that the sparse recovery does not consider the group structure of neural signals. The solution to the multichannel neural recovery using the l_1,2 mixed norm is obtained by replacing the l₁ norm by the mixed norm as

$\begin{array}{cc}{\Psi }_{\mathrm{MC}}\underset{{\alpha }_{\mathrm{MC}}\in R^{d·N}}{\mathrm{argmin}}{{\alpha }_{\mathrm{MC}}}_{1,2}s.t.Y={\Phi }_{\mathrm{MC}}\left({\Psi }_{\mathrm{MC}}{\alpha }_{\mathrm{MC}}\right)& \left(8\right)\end{array}$

For example, let us assume the number of channels is set to N=16 and the signal length is equal to d=1024. The exemplary 16-channel iEEG signal is mapped into a matrix XεR^1024×16 such that the iEEG signals are along the columns of X. We define the operator : R^1024×16→R^1024.16 which transposes X and concatenates the columns of the transposed X to make a vector. The proposed circuit has a compression ratio of 4, therefore 4 measurements are recorded out of the 16 neural channels at each time. The measurement matrix is defined as:

$\begin{array}{cc}{\Phi }_{\mathrm{MC}}=\left[\begin{array}{ccc}{\Phi }_1& 0\dots & 0\\ ⋮& \ddots & ⋮\\ 0& \dots & {\Phi }_{1024}\end{array}\right],{\Phi }_i=\left[\begin{array}{ccc}{\varphi }_i^{1.1}& \dots & {\varphi }_i^{1.16}\\ ⋮& \ddots & ⋮\\ {\varphi }_i^{4.1}& \dots & {\varphi }_i^{4.16}\end{array}\right],& \left(\mathrm{E1}\right)\end{array}$

This means that at each time, the 16 channels will be multiplied by the random matrix φ_i and result in 4 random measurements (see FIG. 14). The elements of φ_i randomly take values in {0, 1}. The measurement vector of the multichannel neural signal, YεR^1024.4 is computed as:

Y=φ _MC (X)   (E2)

The underlying neural signals in channels share similar structures. Hence, the transform domain of the multichannel signal for each neural channel is the same, that is, the sparsity of the multichannel signal reads:

$\begin{array}{cc}{\Psi }_{\mathrm{MC}}=\left[\begin{array}{ccc}{\Psi }_1& 0\dots & 0\\ ⋮& \ddots & ⋮\\ 0& \dots & {\Psi }_{16}\end{array}\right]& \left(\mathrm{E3}\right)\end{array}$

where ψ is the sparsity of each neural channel. We take ψ as a Gabor transform. In addition, the multichannel neural signals have high inter-channel dependency, as the signals recorded by the adjacent channels are delayed or scaled version of each other, depending on the spatial resolution and pitch of the electrodes which indicates the propagation, for example, of neural activity within the brain. The dependent structure of multichannel neural signals suggests the design of a recovery model which exploits the similarity of neural signals. The Gabor coefficients of iEEG signals recorded by adjacent channels in a Gaussian window are shown in FIG. 3(a). The Gabor coefficients are observed to follow similar activity among neural channels for each frequency. Thus, the neural recovery model should employ the cross correlations of iEEG signals to improve the reconstruction quality.

An appropriate model for the multichannel neural signals should highlight the correlated structure of Gabor coefficients, i.e., the model should lead to a sparsity on the number of active frequencies and promote similar activity on the neural channels for the selected frequency (see FIG. 3(a)). The present invention uses a scheme to model such dependent structure, which is the mixed l_1,2 norm and divides the signal into groups such that the elements inside each group have correlated structures. FIG. 3(c) shows the recovered Gabor coefficients using the mixed l_1,2 norm, which yields that the correlated structure of the original multichannel neural signals is well preserved.

The recovered biological signals reconstructed from the compressed measurements and solution to the multichannel neural recovery using the l_1,2 mixed norm is obtained by:

$\begin{array}{cc}\hat{X}=\underset{{\alpha }_{\mathrm{MC}}\in R^{1024·16}}{{\Psi }_{\mathrm{MC}}}\mathrm{argmin}{{\alpha }_{\mathrm{MC}}}_{1,2}s.t.Y={\Phi }_{\mathrm{MC}}\left({\Psi }_{\mathrm{MC}}{\alpha }_{\mathrm{MC}}\right).& \left(\mathrm{E4}\right)\end{array}$

Alternatively, we do not impose the dependencies in data, that is, we instead impose the sparsity on the representation of the neural signals in the multichannel Gabor transform ψ_MC. Instead of the preferred l_1,2 scheme, the recovery process can alternatively be carried out using the l₁ norm.

The sparsity constraint recovers a signal from the compressive measurements under the assumption that the signal can be well represented by a few number of dominant coefficients. Under the RIP condition on the measurement matrix, the sparsity constraint is modeled by the l₁ recovery which looks for a few entries (sparse solution) of a signal. Therefore, the sparse recovery of neural signals from the compressive measurements reads

$\begin{array}{cc}\hat{X}=\underset{X\in R^{d\times N}}{\mathrm{argmin}}{{\Psi }_{\mathrm{MC}}^TX_{\mathrm{vec}}}_1s.t.Y={\Phi }_{\mathrm{MC}}\left(X\right)& \left(\mathrm{E5}\right)\end{array}$

where X_vec is the column-vector form of X which is the concatenation of its columns. In Equation (E5), the l₁ norm (∥•∥₁) promotes a sparse representation of the neural signals. That is the recovered neural signals should have a sparse representation in the Gabor transform, i.e., α_MC=ψ_MC^TX_vec is sparse. In addition, the measurement consistency in the recovery algorithm (Y=φ_MC(X)) pertains to obtaining a signal X which is in accordance with the measurements Y through the measurement matrix φ_MC. Therefore, Equation (E5) looks for a signal X which is sparse in the Gabor transform and satisfies the measurements received from the decoder.

As explained, the sparse assumption on the neural signals promotes component wise sparse solution and cannot encode information about the patterns of neural coefficients in the Gabor transform. As shown in FIG. 3, it is clearly evident that the significant coefficients are organized along horizontal lines. Such structure cannot be modeled using the coefficient-wise sparsity. Therefore, we can improve the reconstruction performance of the sparse recovery by fusing this knowledge into the recovery model.

The natural way to incorporate the pattern of the signals in the sparse model is to group the coefficients into blocks such that the coefficients within a group are compared together for selection or setting to zero. In order to index the coefficients and their corresponding groups, each coefficient is indexed by a pair of (g, m), where g is the group index and m is the index of the coefficients within group g. The mixed l_1,2 norm leads variables in the same group to be jointly selected or set to zero. To model the correlation in neural signals, the representation of neural signals in Gabor transform are grouped, where the groups are Gabor coefficients per frequency bin of Gabor transform (horizontal lines in FIG. 3). The mixed l_1,2 norm recovery is expressed by previous Equation (E4) where ∥•∥₂ models group sparsity.

Basically this approach groups the representation of the neural signal in the Gabor transform (α_MC) along each frequency bin to impose the specific pattern of the Gabor coefficients. Similar to the sparse recovery, the measurement consistency guarantees that the recovered neural signal agrees with measurements acquired by the encoder. It should be noted that, in the mixed norm, recovery ψ_MCα_MC is used instead of X in the measurement consistency term. The reason is that the mixed norm promotes the pattern of the representation of the neural signals in the Gabor transform, i.e. α_MC, which means it recovers the representation of the neural signals in the Gabor transform. However, the sparse recovery directly looks for the neural signal X and promotes its sparsity in the Gabor transform. In the mixed norm recovery, the neural signal is recovered by {circumflex over (X)}=ψ_MC{circumflex over (α)}_MC, where {circumflex over (α)}_MC is the solution to the mixed norm minimization problem.

III. Circuit Implementation

FIG. 2 illustrates an exemplary system-level view of the proposed multichannel compressive sensing method used in an implantable neural recording interface, where the neural signals sensed at the electrode sites are amplified, randomly projected, summed up and digitized through a single on-chip ADC. An RF unit placed within a burr hole in the skull transmits the compressed and digitized data originating from several recording chips to an external receiver and powers the implanted system.

FIG. 2 illustrates a system 1 for compressing a plurality of biological signals and for recovering biological signals. The system 1 includes a plurality of implantable sensors (or devices) 3, an implantable transmitter 5, a receiver 7 and a processor 9.

The implantable sensor 3 includes a plurality of electrodes 11 each of which is configured to capture or measure a biological signal, as well as a plurality of amplifiers 15. Each amplifier 15 comprises a low-noise amplifier with a band-pass transfer function and is connected to a single electrode 11 to amplify the signal captured by that electrode 11.

The implantable sensor 3 further includes a plurality of low-pass filters 17 (see FIG. 4) to limit the high cut-off frequency of the amplified captured signal. Each low-pass filter 17 is connected to a single amplifier 15 to receive the amplified captured signal.

The implantable sensor further includes a plurality of additional amplifiers 21. Each additional amplifier 21 is connected to a single low-pass filter 17 to further amplify the signal provided by said low-pass filter 17.

The implantable sensor additionally includes a plurality of buffered sample-and-hold circuits 23. Each buffered sample-and-hold circuit 23 is connected to a single additional amplifier 21 to receive the signal amplified by said additional amplifier 21.

The implantable sensor additionally includes a random summing circuit 25 connected to receive each of the signals provided by the electrodes 11 that each have been processed by an amplifier 15, a low-pass filter 17, an additional amplifier 21 and a buffered sample-and-hold circuit 23.

The random summing circuit 25 is configured to randomly select samples of these processed signals and sum these samples to provide a multichannel measurement signal.

The implantable sensor 3 further includes a single analog-to-digital converter 27 connected to the random summing circuit 25 to receive the multichannel measurement signal. The analog-to-digital converter 27 is configured to digitize the multichannel measurement signal to output a digital compressed signal. The compressed signal is provided to the implantable transmitter 5.

The implantable transmitter 5 includes an RF circuit and an antenna and is configured to wirelessly transmit the compressed signal to the receiver 7. The implantable RF chip 5 is further configured to provide energy to the implantable sensors 3.

The receiver 7 includes an RF circuit and an antenna to receive and process the transmitted data. The processor 9 is configured to receive the compressed signal from the receiver 7 and to process the compressed signal to reconstruct the captured biological signals.

In order to realize the CS acquisition scheme proposed in Section II, the architecture shown in FIGS. 2 and 4 is designed and implemented in a 1P6M 0.18 μm CMOS technology. The main focus of this design consists of accommodating a large number of recording units into the available die area, while preserving sufficiently low noise and low-power performance. Low power consumption and compact area are crucial in high-density implantable recording systems.

A. Recording Channels

The fabricated integrated circuit includes 16 recording channels. Each channel consists of a low-noise amplifier with a band-pass transfer function 15, an additional low-pass filter 17 to limit the high cut-off frequency, a second gain stage 21, and a buffered sample-and-hold circuit 23. The differential outputs of all channels individually connect to the summing stage and randomly accumulate at the output of this stage. The result is then digitized through a single ADC 27.

As described above in Section II and shown in the exemplary embodiment of FIG. 1, every set of 16 channels of a pre-determined time-window (time sample) are multiplied by a random matrix φ_i of size 4×16, which generates the four corresponding measurements. This operation then occurs within 1024 time samples over the array. Each row of the matrix is multiplied by the same neural signal vector, necessitating a holding operation at the output of the channels. Following the amplification and filtering in individual channels, the sampled and held differential outputs of every 16 pixels connect to the summing stage 25 (FIG. 4(b)) and randomly accumulate at the output of this stage 25. The outputs are controlled by the random sequences which are specific to each channel. Multi-output sequence generation is achieved by XORing the multiple outputs of maximal-length pseudo-random binary sequence (PRBS) generators (FIG. 4(c)) as will be explained in further detail below.

Depending on the instantaneous value of the random sequence, the output of the channel is summed at the output of the summing stage 25. For instance, assuming a smaller number of 4 channels for the sake of simplicity, and for φ_R1=1, φ_R2=0, φ_R3=1, and φ_R4=1, the output of the summing stage is calculated as:

V _summed =V _out,1 +V _out,3 +V _out,4  (E6)

This summation is equivalent to the matrix multiplication presented in Section II. In total, since only 4 measurements are collected from 16 channels, a compression ratio of 4 is achieved. A variable voltage gain in the summation stage 25 is enabled through the controlling switches in series with the feedback capacitors. Due to the randomized summation at this stage, the programmability of the gain is crucial. The gain stage 29 preceding the ADC 27 provides an additional gain of three, to perfectly accommodate the full-scale input range of the ADC 27.

A three-stage configuration is used in each channel [22], in order to minimize the total die area and provide the desired amplification and filtering of the input signal.

1) Low-Noise Amplifier 15:

An area-efficient T network-based capacitive feedback amplifier [23] with moderate-sized input capacitors is used as the front-end gain stage G₁, which provides a mid-band gain of 29.8 dB [FIG. 5(a)]. The mid-band gain of this stage is realized by multiplying two capacitive ratios. This potentially provides a high closed-loop gain in a single stage. Using this topology, the total size of the capacitors is smaller than the size of capacitors in a conventional capacitive feedback topology [24]. Four back-to-back MOS devices biased in subthreshold region are used to implement the high-value feedback resistors with sufficient linearity for creating a low-frequency high-pass pole [FIG. 4(a)]. The variation on the high-value resistance over the voltage swing across the resistor is 1.5% at 200 mV and remains smaller than 2% up to a voltage swing of 600 mV across the resistor. Owing to the series connection of the high-value resistors in a symmetric combination, the equivalent resistance exhibits symmetric variations around the quiescent point in all process corners. The simulated high-pass cut-off frequency varies in the range of 14-118 Hz, under the worst-case process corner, supply voltage and temperature variations.

The differential mid-band gain of this stage is calculated as

$\begin{array}{cc}{A}_M=-\left(\frac{C_1}{C_2}\right)\left(\frac{2C_4+C_2+C_3}{C_3}\right)& \left(9\right)\end{array}$

In general, the smaller the input capacitance in the feedback loop is, the larger the ratio of the OTA (operational transconductance amplifier) noise referred to the input of the LNA will be, since the OTA's input parasitics become comparable to C₁. To tackle this issue, the additional gain provided by the second capacitive ratio is selected small compared to the first term in (9) to satisfy the low-noise operation as well. In this design, C₂=C₃=200 fF, C₁=1.4 pF and C₄=400 fF, resulting in C_tot=4 pF. The conventional topology [24] requires a total capacitance of 64×200 fF≈12.8 pF to achieve a similar mid-band gain.

A second benefit of replacing the very large input capacitance by a moderate one is that the larger input impedance provided by a moderate input capacitor reduces the effect of attenuation of cortical signals in the electrode-channel interface.

A folded-cascode OTA with a continuous-time common-mode feedback (CMFB) circuit is implemented in the LNA [FIG. 4(a)]. Through the dc path provided by the large-value feedback resistors, the same CM voltage as V_CM is generated at the input gates of the OTAs used in G₁ and G₂. The total bias current of the OTA is 7 μA. The simulated passband of the LNA ranges from 28 Hz to 144 kHz. The linearity performance of the LNA is described by the THD metrics which is 0.24% for a 2 mV input signal. This LNA consumes 8.4 μW of power, corresponding to 89% of the total power consumed by the channel.

The ac-coupled architecture provided by the capacitive feedback topology enables the amplifier to reject the large dc offsets (as large as 1-2 V [24]) which are commonly generated in an electrode-tissue interface. The common centroid layout of the input differential pair in the LNA and the passive components such as input and feedback capacitors results in improved matching and offset performances, which are mainly limited by the front-end LNA. The measured input-referred offset of the stand-alone channel is 0.85 μV.

2) Filter 17, Amplifier 21 and S/H 23:

The commonly used low bandwidth of interest (less than 2 kHz) for capturing iEEG signals (e.g., for epileptic activity detection) requires additional low-pass filtering after the LNA. Limiting the bandwidth using a low-pass filter stage with minimal power and noise costs is more beneficial to limit the die area per channel than aggressively increasing the C_L of the LNA. A first-order source-follower based low-pass filter (adapted from [25]) is used which achieves sufficient linearity at a small bias current [FIG. 4(a)]. The DC-gain loss due to the bulk transconductance which is inherent to the source-follower architecture is reduced by a source-to-bulk connection. The internal feedback of the source-follower circuit and processing the signal in voltage domain increases the linearity range of the filter.

The presented filter exhibits a THD of 0.08% (equal to 10-11 bits of linearity) for a filter input signal of 60 mV_p-p (or 2 mV at the input of a channel) consuming a bias current of 5.4 nA. The cut-off frequency is 1.9 kHz and is tunable by the current.

A second gain stage 21 [G₂ in FIG. 4(a)] provides an additional gain of dB using a conventional capacitive feedback architecture. The power consumption of the second gain stage is negligible (0.72 μW) compared to the front-end LNA, thanks to the relaxed noise requirements. Using a folded-cascode OTA architecture, an output voltage swing as large as 200 mV_p-p is achieved in the second gain stage. The size of the transistors in this OTA are selected smaller compared to the OTA used in the front-end LNA, thanks to the relaxed noise and matching requirements.

The amplified and band-pass filtered signal of each channel goes through a sample-and-hold (S/H) stage 23 followed by a source-follower buffer to keep the signal constant during the consecutive M measurements (M=N/CR in this case). The S/H circuit is controlled by the signal SH_Ch which is (M+1) times slower than the signal of the ADC and is generated using a single (M+1)-bit shift register [FIG. 4(b)]. The output common-mode voltages of the LPF and BUF are defined by the gate-source voltage of the PMOS transistors which are located at their input, knowing that the output bias voltage of the preceding stages are defined through the CMFB of G₁ and G₂. The source-to-bulk connected source-follower buffers at the output of each channel exhibit a THD of 0.12%, which equals to 9-10 bits of linearity for a 200 mV_p-p input signal. The total power consumption of the LPF, buffer and in-channel biasing circuitry is less than 0.3 μW.

The required settling time to guarantee B-bit performance imposes the following condition at the output of the second gain stage, prior to the S/H:

$\begin{array}{cc}{}^{-\left(\frac{1/\left(2\mathrm{fs}\right)}{\tau }\right)<0.5\times 2^{-B}}& \left(10\right)\end{array}$

for B=8 and f_S5=4 kS/s this condition results in

$\begin{array}{cc}{}_{-3dB}=1/2\pi \tau >\frac{\left(B+1\right)\ln 2}{\pi }{}_s\approx 1.98{}_s\approx 8\mathrm{kHz}& \left(11\right)\end{array}$

in which f_{−3 dB} represents the bandwidth of the circuit when the sampling capacitor is connected. Assuming a sampling capacitor of 0.4 pF, the achieved bandwidth is 55 kHz, consuming a low bias current of 0.6 μA.

B. Randomly Controlled Summing Stage 25

The sampled signals of channels of the array connect to the summing stage at the sampling phase (φ_S3) which follows the two in-phase events φ_S1 and φ_S2. By applying a proper timing strategy φ_S1 comes before φ_S2 and φ_S2 before φ_S3) as presented in FIG. 4(b) and using bottom-plate sampling, it is possible to substantially reduce the effect of channel charge injection of the switches. The effect of clock feedthrough is reduced by the differential implementation. A variable voltage gain is achieved through the controlling switches in series with the feedback capacitors. Due to the randomized summation at this stage, the programmability of the gain is crucial. The gain stage preceding the ADC 27 provides an additional gain of three to perfectly accommodate the full-scale input range of the ADC 27. A hybrid two-stage class A/AB topology [28] is used as the OTA in this stage, which provides the desired rail-to-rail output swing.

The operation of the summing stage is as follows. In sampling mode, φ_S1, φ_S2 and φ_S3 are on, allowing the differential voltage across the two sampling capacitors (C_S) at the output of each channel to track the differential output voltage of that channel. In summation mode (φ_S1, φ_S2 and φ_S3 are off), the charge stored on the sampling capacitors of those channels with random value equal to one are transferred to the capacitors in the feedback path (C_f). This enables the summation of the sampled values of channels, based on the value of the corresponding random sequence.

A reasonable lower bound for the bandwidth of OTA used in the summing stage can be calculated from (10) which equals 50 kHz at a sampling rate of (M+1) f_S=20 kS/s. The stability and speed of the feedback loop is guaranteed for the worst case where all random values are equal to one, while a single feedback capacitor is connected which corresponds to A_M,INT=N, for equal unit capacitors and equal inputs.

1) System Resolution:

Assuming the worst-case situation in which all channels of the array are summed together while all N controlling random values are equal to one, the following constraints on the signal headroom and noise prior to the ADC will exist:

NV _in,sig A _M≦2VDD   (12)

NV _n,rms ² A _M ²≦(2VDD)²/12·2^2By   (13)

where A_M is the total mid-band gain from the input of the channels to the input of the ADC, V_in,sig is the peak-to-peak amplitude of the input signal, V_n,rms is the rms value of the input-referred noise of each channel and N is the number of channels.

Having

$V_{\mathrm{in},\mathrm{rms}}=\frac{V_{\mathrm{in},\mathrm{sig}}}{2\sqrt{2}}$

for a sinusoidal waveform, results in B_y≈B_sig+log₂√{square root over (N)}−0.58. Generalizing this equation to any arbitrary waveform with

$V_{\mathrm{in},\mathrm{rms}}=\frac{V_{\mathrm{in},\mathrm{sig}}}{K}$

yields

$\begin{array}{cc}{B}_y\approx {\log }_2\frac{V_{\mathrm{in},\mathrm{sig}}}{V_{n,\mathrm{rms}}}+{\log }_2\sqrt{N}-1.78& \left(14\right)\end{array}$

which is independent of the parameter K. Considering a background neuronal noise of 5-10 μV_rms [26] and a typical amplitude of surface cortical signals of up to 1 mV and adding some extra margin, B_sig and B_y are set to 8 and 10 for 16 channels. This calculation excludes the rms thermal noise of the electrodes which can be in the order of 10-20 μV [27], depending on the size, material and operating temperature of the electrodes. In reality, this noise further degrades the dynamic range of the input signal and the effective number of bits achievable at the system level.

The effective compression ratio of the proposed CS topology is then approximated by

$\begin{array}{cc}{\mathrm{CR}}_{\mathrm{eff}}\approx \frac{{\mathrm{NB}}_{\mathrm{sig}}}{\left(M+1\right)\left(B_{\mathrm{sig}}+{\log }_2\sqrt{N}\right)}& \left(15\right)\end{array}$

2) Large-Scale Implementation:

The imposed requirement on the ADC resolution degrades the power efficiency of the system at large number of channels and sets an upper limit for the maximum number of channels connected to the summing stage prior to the ADC. Thus, the model shown in FIG. 6 is adapted for large arrays. The digital outputs of 16-channel blocks are summed together by a digital accumulator with sufficiently large number of bits. The power and area cost of adding the required number of bits to the resolution of the accumulator is significantly less compared to the cost of increasing the resolution of the ADC. Designing an ADC for target resolutions higher than 10 bits requires additional topological modifications which are commonly achievable by consuming more power. Using this method, the proposed CS concept is still more area- and power-efficient for large arrays than single-channel approaches.

In this model, the limit on the compressed array size is imposed by the acceptable power efficiency of the summing stage and ADC which are sampled at a rate of

$\left(1+\frac{N}{\mathrm{CR}}\right){}_s$

with f_S being the Nyquist sampling rate. The multichannel system is then divided into sub-blocks of N-channels, with N being the optimum number of channels to be compressed into a single data stream. Each sub-block is encoded to a digital data stream which after reconstruction, generates the signals originated from the channels constituting that sub-block.

3) Random Matrix Generator:

In order to guarantee an efficient implementation of compressive sensing, the power and area cost of CS circuits including the measurement matrix generator must be negligible compared to the rest of the integrated circuit. In a single-channel approach, each channel is loaded with m sequences (building the rows of the measurement matrix explained in (1)), whereas in the proposed model, each channel needs to be driven by only one sequence. As shown in (3), the measurement matrix supporting the consecutive M measurements for recovering each sample of individual channels is filled by the corresponding M values of the in-channel sequences.

This approach circumvents the need to place a memory to store the elements of the measurement matrix.

As shown in FIG. 4(c), multi-output sequence generation is achieved by XORing the multiple outputs of maximal-length pseudo-random binary sequence (PRBS) generators [29]. For a recording array of 4×4 and a value of M equal to 4 (resulting in CR=16/4), the 16 sequences driving the individual channels are generated by XORing the states of a 4-bit PRBS generator with another 5-bit PRBS generator. As opposed to the single-channel compressing system which has to be physically designed for a specific predefined and redesigned by varying the compression ratio, the proposed scheme is easily adaptable for different values of M by adjusting the clock frequency.

4) Noise Analysis:

Power, area and noise are the three major performance metrics of an implantable system. Ideally, the noise performance of the system is limited by the background extracellular noise and by the noise of the electrodes. In addition to the low-noise amplifier at the front-end of each channel, the noise induced by the switched capacitor summing stage should be minimized. While the effect of flicker noise can be reduced by using large input devices (generally PMOS), the thermal noise induced by the switching circuits can affect the total noise of the system, prior to the ADC. A comprehensive sampled noise analysis based on an approach similar to [30] is presented to give an insight into the appropriate values of the design parameters of the summing stage. As a general noise reduction technique, the input differential pair of the folded-cascode OTA used in the front-end LNA is biased in subthreshold region [31].

This results in a large g_m/I_D of the input transistors and reduces the input-referred noise of the OTA. The mean-square value of the total thermal noise at the output of each channel can be approximated by integrating the PSD of OTA noise at the input [31], shaped by the low-pass transfer function of the loop [see the half-circuit model shown in FIG. 5(b)], and fed into the low-pass filter and second gain stage, resulting in

$\begin{array}{cc}\stackrel{\_}{v_{n,\mathrm{out}}^2}\approx S_{n,\mathrm{op}}·\frac{A_{M,\mathrm{tot}}^2}{4\tau }=\frac{4\mathrm{kT}}{\kappa g_m}·\frac{A_{M,\mathrm{tot}}^2}{4\tau }& \left(16\right)\end{array}$

where k is Boltzmann's constant, T is the absolute temperature, κ is the reciprocal of the subthreshold slope factor,

$A_{M,\mathrm{tot}}\approx \frac{1}{{\beta }_1{\beta }_2},$

1/β₁ is obtained from (9) and 1/β₂ is the mid-band gain of the second gain stage. Assuming

${\tau }_1=\frac{C_L}{{\beta }_1g_m}$

the settling time constant at the output of the LNA with a load capacitor of C_L and an input transconductance of g_m, and

${\tau }_2=\frac{C_{\mathrm{LPF}}}{g_{m,\mathrm{LPF}}}$

the time constant at the output of the LPF, τ₂>τ_i and (16) yields

$\begin{array}{cc}\stackrel{\_}{v_{n,\mathrm{out}}^2}\approx \frac{\mathrm{kT}·A_{M,\mathrm{tot}}^2·g_{m,\mathrm{LPF}}}{\kappa g_mC_{\mathrm{LPF}}}& \left(17\right)\end{array}$

The equivalent half-circuits of the summing stage during the sampling and integrating phases are shown in FIG. 7. The PSD of the thermal noise generated on the sampling capacitor (C_S) which is due to the switch placed in-series with C_S and during φ_S3 can be written as [30]

$\begin{array}{cc}{S}_v\left(f\right)=\frac{4{\mathrm{kTR}}_{\mathrm{on}}}{1+{\left(2\pi f{\tau }_0\right)}^2}& \left(18\right)\end{array}$

Here, R_on the on resistance of the switch and τ₀ is the time constant of the C_S branch during sampling (φ_S3), which is expressed as

$\begin{array}{cc}{\tau }_0\approx C_S·\left(R_{\mathrm{on}}+\frac{R_{\mathrm{on}}}{2+g_mR_{\mathrm{on}}}\right)& \left(19\right)\end{array}$

The corresponding noise integrated from 0 to

$\frac{\mathrm{kT}}{\left[C_S\left(1+\frac{1}{2+g_mR_{\mathrm{on}}}\right)\right]}$

which summed up to the non-significant noise terms generated by the two switches φ_S1 and φ_S2 can be estimated as kT/C_S.

During the second phase (φ_S3 is open), the equivalent time constant of this circuit can be approximated by

$\tau =C_S\left(R_{\mathrm{on}}+\frac{1}{g_m}\right).$

The mean-square value of the switching noise assuming that in the worst case, φ_Ri is equal to one for i=1, . . . , N, is calculated as [FIG. 7(b)]

$\begin{array}{cc}\stackrel{\_}{v_{n1}^2}\approx \frac{4{\mathrm{kTR}}_{\mathrm{on}}}{4\tau }=\frac{\mathrm{kT}/C_S}{1+1/x}& \left(20\right)\end{array}$

The parameter x is introduced as x=R_on g_m. The noise power in C_S due to the op-amp when φ_S3 is open is found as

$\begin{array}{cc}\stackrel{\_}{v_{n2}^2}\approx \frac{4\mathrm{kT}/\kappa g_m}{4\tau }=\frac{\mathrm{kT}}{\kappa C_S\left(1+x\right)}& \left(21\right)\end{array}$

Thus, the total input-referred noise of the differential summing stage can be expressed as

$\begin{array}{cc}\stackrel{\_}{v_{n,m}^2}\approx \frac{2\mathrm{kT}}{C_S}+\frac{2\mathrm{kT}/C_S}{1+1/1x}+\frac{2\mathrm{kT}}{\kappa C_S\left(1+x\right)}=\frac{\mathrm{kT}}{C_S}\left(\frac{4x+2+2/\kappa }{x+1}\right)=\frac{\mathrm{kT}}{\tau g_m}\left(4x+2+2/\kappa \right)& \left(22\right)\end{array}$

referred to the input of each summing branch (or equivalently to the output of each channel). Based on this equation, the noise is minimized for x<<1. The total noise power calculated in (22) should be smaller than the output noise power of channels calculated by (17) which satisfies the noise requirement prior to the ADC 27. There is a clear trade-off between the summing stage's noise and the circuit area which is proportional to C_S. However, considering the extra margin assumed in calculating the system resolution based on (14), and accounting for the electrode and background noise, enables letting the noise due to this stage be as large as the noise of channels, keeping in mind that additional noise reduction does not improve the effective number of bits but further degrades the area efficiency of the implantable system. The typical value of the in-band input-referred noise power due to the LNA is more than 10 times smaller than the electrode noise power for this application.

With this assumption, a minimum value of C_S equal to 200 fF is required to guarantee the proper performance of the summing stage. For an optimal design, the maximum permissible value of τ based on (10) can be substituted into

$\tau =\frac{C_S\left(1+x\right)}{g_m}$

resulting in the lowest g_m which can fulfill the noise and bandwidth requirements of this stage. The assumed constraint on (i.e., x<<1) determines the minimum size of the switches in this case. For equally-sized capacitors, these switches are selected (M+1) times larger than the in-channel S/H switches which operate at a lower frequency.

C. Analog-to-Digital Converter 27

Following the random summation and an additional amplification, the random accumulated value is digitized using a single analog to digital converter 27 (FIG. 4b). The main advantage of the proposed topology is that, as opposed to conventional CS architectures, the random accumulation and ADC 27 are implemented only once per 16 channels, resulting in improved power and area efficiency of the system.

The stringent area and power constraints of the implantable system motivate the compact and energy-efficient implementation of the ADC 27. Based on system-level requirements, an ADC with 10 bits of resolution and a sampling rate of 20 kS/s translates into a data recorded in each channel with 8 bits of resolution and a sampling rate of 4 kS/s. The SAR ADC is a popular architecture which enables low-power data conversion for medium resolution/speed applications. A binary-weighted capacitive array with attenuation capacitor [FIG. 4(b)] is used which enables the compact implementation of the ADC. The potentially small input capacitance of this array results in relaxed specifications of the stage preceding the ADC, in terms of bandwidth and power consumption. The total required capacitance of the attenuated array is times smaller than a conventional binary-weighted array where is the number of bits.

As shown in the timing diagram of FIG. 4(d), the data sampled from a channel is kept constant during the M randomized summations and consecutive digitizations through the ADC 27. Thanks to the low bandwidth of iEEG signals, the PRBS generator and ADC are clocked at a rate faster than the sampling frequency of the individual channels. This allows the computations to be done within the input sampling period. All the required signals are generated using a single external clock of 400 kHz, as shown in the timing diagram of FIG. 4(d). The sample-and-hold signal of the ADC is generated at a rate equal to 1/20 of the external clock, which enables 10-bit conversion of the summed value.

Digitization occurs during the half-cycle in which random sequences are zero [shown in FIG. 4(d)], thus converting the previous accumulated value. At the same time, the sampling signals of the summing stage [φ_S3 and also the in-phase signals φ_S1 and φ_S2 in FIG. 4(b)] are equal to one, which resets the output of the summing stage and stores the corresponding channel's output for the following accumulation phase. During the next half-cycle, the sampled values at the input branches of the integrator which are stored on the capacitors C_S, are summed together based on the value of the random sequence controlling that branch. Thus, the output of the summing stage at the rising edge of the φ_S3 represents the randomized summation of the channels' samples which must be converted to the digital bit stream, using the ADC.

IV. Experimental Results

The measured frequency response at the output of G₂ and input-referred noise of the stand-alone channel are shown in FIGS. 8 and 9. The high-pass pole is measured at 39 Hz, while the simulated cut-off frequency is 28 Hz. Thus, the HP-pole differs by 40% with respect to the desired value. The discrepancy between the simulated and measured high-pass pole is due to the inaccurate model of the transistors in weak inversion region, and the extra parasitics which affect the total capacitance of the feedback path. A more precise control on the high-pass cut-off frequency can be achieved by adjusting the feedback capacitor and resistor using digital words as shown in [37].

The input-referred noise density at the channel input is 25 nV/√Hz at 1 kHz. The input-referred noise integrated over the signal bandwidth is 3.2 μV_rms, while it increases to 4.2 μV_rms when integrated from 1 Hz to 100 kHz. The Noise Efficiency Factor (NEF) of the analog front-end (including G₁, LPF and G₂) is defined as [32]

$\begin{array}{cc}\mathrm{NEF}=V_{n,\mathrm{rms}}·\sqrt{\frac{2I_{\mathrm{tot}}}{\pi ·U_T·4\mathrm{kT}·\mathrm{BW}}}& \left(23\right)\end{array}$

The measured NEF is equal to 4.12 and 3.23 for the noise integration bandwidths of 1 Hz-100 kHz and passband of the signal, respectively.

Table I presents the performance summary of the analog front-end (AFE) and ADC which are compared with published works.

TABLE I
COMPARISON OF THE AFE AND ADC PERFORMANCE WITH PUBLISHED LITERATURE
Parameter	[38]	[39]	[37]	[40]	[41]	[42]	[23]	[43]	[44]	This Work
Technology [μm CMOS]	0.35	0.13	0.13	0.18	0.35	0.35	0.35	0.13	0.13	0.18
Bandwidth [Hz]	10-5k	0.023-11.5k	167-6.9k	10-7.2k	1-5k	217-7.8k	1-8.5k	1-5k	0.1-5k	39-1.9k
Gain [dB]	33	38.3	47.5	39.4	34	45.7	38.1	54-60	54-60	43.8
Input-Referred Noise [μVrms]	6.08	1.95	3.8	3.5	7	4.43	13.3	5.1	6.5	4.2
NEF	5.55	2.48	2.16	3.35	4.6	2.16	7.87	4.4	7.2	4.12
AFE Area [mm2]	0.020	—	<0.080	0.062	0.020	—	0.056	0.045	<0.090	0.040
CMRR	60	63	83	70.1	—	58	74	75	75	59.8
PSRR	—	63	—	63.8	—	40	55	—	—	—
AFE Power Consumption [μW]	8.4	12.5	1.92	7.92	4.2	1.26	6	8.5	4.5	9.4
ADC Sampling Fequency [kS/s]	111	10-100	22.5	—	—	2.56	—	≦100	57	20
ENOB	6	6.2	7.65	—	—	8.3	—	7.6	7.8	9.2
INL [LSBs]	—	—	−0.45	—	—	1.52	—	0.7	—	−0.76
DNL [LSBs]	—	—	−0.71	—	—	0.89	—	0.6	—	−0.37
ADC Power Consumption [μW]	2.77	<1	0.5	—	—	31.3	—	1.5	1.8	2.6

The microphotograph of the fabricated chip is shown in FIG. 10(a). The total current consumption of the chip including the buffers and bias generators is 140 μA drawn from a 1.2 V power supply, corresponding to effective current of 8.75 μA per channel. The achieved power density of the system is 7.2 mW/cm², significantly below the safety limit of 80 mW/cm² [33] for an implantable system. The contribution of different blocks of the system to the total power consumption is shown in FIG. 10(b). The area occupation and power consumption of each block of the system are shown in Table II.

TABLE II
POWER CONSUMPTION AND AREA
USAGE OF INDIVIDUAL BLOCKS
Parameter     Value
PChannel      9.4 μW
PSummingStage 8.4 μW
PGainStage    4.2 μW
PADC          2.6 μW
PPRBS         0.03 μW
AChannel      220 μm × 180 μm
ASummingStage 290 μm × 150 μm
AGainStage    150 μm × 100 μm
AADC          290 μm × 150 μm
APRBS         90 μm × 80 μm

In order to demonstrate the effectiveness of the proposed acquisition model, a long segment of multichannel iEEG signal recorded from subdural strip and greed electrodes implanted on the left temporal lobe of a patient with medically refractory epilepsy have been used as the input.

The signals are recorded during an invasive pre-surgical evaluation phase to pinpoint the areas of the brain involved in seizure generation and to study the feasibility of a resection surgery. This data includes minutes of pre-ictal, ictal and post-ictal activities sampled at 32 kS/s, using Neuralynx. The signals recorded by 16 adjacent channels of a greed of the electrodes are applied into the proposed CS system.

A. Recovery Performance

Many biological signals can be sparsely represented in either Gabor or wavelet domains [8]. We employ Gabor transform as the sparsity domain of neural signals for multichannel neural recovery based on sparse and mixed norm methods. The recovery SNR of the reconstructed signal ({circumflex over (x)}) with respect to the original signal (x) is calculated from

SNR=−20 log₁₀(∥x−{circumflex over (x)}∥₂/∥x∥₂)   (24)

for each recording channel (e.g., represents the recovery SNR_CH1 of first channel). The mean SNR of 16 channels are averaged over 100 blocks of the signal, as shown in FIG. 11. The performance of the circuit is validated for low-voltage fast activities which are shown to be associated with seizure onset. The reconstructed signals versus the original signals corresponding to one block of a single channel data using l₁ and l_1,2 recovery are shown in FIGS. 12(a) and (b). The length of each compression block (d) is equal to 1024 samples and is equivalent to 256 msec at a 4 kHz sampling frequency. The digitized data after ADC is used for recovery. As shown in these figures, applying the recovery on the compressed data produced by the adjacent channels results in an improved recovery performance, compared to the sparse recovery. The averaged SNRs using the l₁ and l_1,2 recovery are 16.64 dB and 21.80 dB, respectively. Based on the statistical analysis reported in [34], a minimum SNR of 10.45 dB (corresponding to a PRD of 30%) is acceptable to maintain the diagnostically important data in the recovered signal, e.g., for successful seizure detection. Reducing the number of measurements to M=1, i.e., CR=16 results in average SNR=13.72 dB, using l_1,2 recovery. Thus, the system is able to successfully recover low-voltage iEEG signals compressed by a ratio as high as 16. FIG. 13 presents the average reconstruction SNR for sparse and joint recovery for different compression ratios. The achieved compression ratios vary within the range of 16/15 up to 16, corresponding to CR=16/M, where M is an integer number between 1 and 15.

As confirmed by the average SNR, the system is potentially able to recover the signal over the entire recording period, with some tolerable loss (i.e., SNR>10.45 dB). However, the amplitude and frequency of the recorded signals can significantly vary, depending on the distance between the microelectrodes and their surface area [35]. The amplitude of the very high frequency oscillations (250-500) recorded using macroelectrodes [36] is much smaller (5-30 versus 100-1250 μV) than human fast ripples recorded from smaller microelectrodes [35]. The amplitude of the fast ripples recorded by the high-density arrays will expectedly fall within the range of tens-hundreds of microvolts, which is efficiently recovered at the output of the system, as shown in FIG. 12.

The required time for the reconstruction of the 1024-length epochs of the multichannel signal is 1.12 second per channel, using a 2.66 GHz processor with 4 GB of RAM. To achieve a real-time performance, the speed of the reconstruction could be improved by hardware implementation of the algorithm on FPGA and using custom acceleration techniques.

B. Effect of Circuit Non-Idealities and Non-Adjacent Channels

A second database consisting of multichannel intracranially recorded signals of the slices of a rat somatosensory cortex under bicuculline, which blocks the synaptic inhibition and consequently mimics the epilepsy, is applied to the CS recording system. This signal includes epileptiform burst activity and extracellularly detected spikes. However, the verifiable signals of this database are associated with electrodes randomly located on the array. Consequently, these channels exhibit limited synchronous activity during the seizure, compared to the previous database. This effect is reflected in relatively lower recovery SNR of neural signals presented in Table III. SNR is evaluated for each channel and for the multichannel signal, by comparing X_vec with the reconstructed multichannel data stream (defined as SNR_T).

TABLE III
RECOVERY QUALITY IN THE PRESENCE
OF NOISE (SNRS ARE IN DECIBELS)
	Gabor Transform, l1 recovery, CR = 4
	x QN a	✓ QN	x QN	✓ QN	MAT
Performance Metric	x cktNb	x cktN	✓ cktN	✓ cktN	LAB
SNRCH1	14.83	14.64	14.75	14.32	15.12
SNRT	10.82	10.52	10.76	10.23	10.97
a Excluding the quantization noise.
bExcluding the noise of the circuit.

In order to study the effect of circuit non-idealities (such as quantization and thermal noise) on the recovery performance, a comparison of SNR is also presented in Table III. The reconstruction results are compared by including and excluding different noise sources in simulations. The results are compared to the recovery performance of the compressed signal generated by matrix multiplication in MATLAB, using the same matrix as the output of the on-chip PRBS generator. CS can improve the attainable signal fidelity in the presence of sensor noise as shown in [45]. Although the reconstruction performance of a CS system is not as good as a simple quantizer for noiseless inputs [46], for more practical noisy signals recorded by the sensors, CS achieves a better performance, i.e., lower energy and improved PRD (Percentage Root-Mean Squared Difference) [45].

The CS system filters some of the input noise during reconstruction [45], and consequently is a correct choice for noisy environments such as a neural interface. Otherwise expressed, the recovery algorithm discards the coefficients below a certain threshold in the sparse representation of the signal. The discarded coefficients can be interpreted as filtered noise. The recovery performance of the proposed system is marginally affected by the quantization noise of the ADC, as confirmed by the results of simulations presented in Table III.

Excluding the circuit noise in simulations (thermal and flicker) results in a negligible improvement of the recovery performance which confirms the robustness of the CS system against non-idealities induced by the circuit. Consequently, the specifications related to the resolution of the ADC, the required noise performance of the analog front-end and the summing stage preceding the ADC and therefore the total power consumption and area of the chip can be further relaxed without jeopardizing the recovery performance.

C. Comparison and Future Work

Table IV summarizes the performance of the system and presents a comparison with published works.

TABLE IV
COMPARISON OF SYSTEM PERFORMANCE WITH PUBLISHED LITERATURE
Parameter	[8]	[37]	[47]	[48]	[49]	[50]	This Work
Technology [μm CMOS]	0.09	0.13	0.5	0.18	0.5	0.5	0.18
Power supply [V]	0.6	1.2	3.3	1.8	—	3	1.2
Compression method	DCS	PWL Spike det.	Spike det.	AP det.	DWT Spike det.	Spike det.	MCS
Number of channels	1	1	100	16	32	32	16
Compression area per channel [mm2]	0.103	0.080	<0.160	>0.0475	0.18	0.12	0.008
Compression power per channel [μW]	1.9	1.18	27	>96	95	75	0.95
Sampling rate per channel [kS/s]	≦20	90	15	30	25	20	4
Compression ratio	≦10	125	150	48	≦20	12.5	≦16

In this table, compression power and area refer to the extra power consumption and area usage of the signal digitization, compression and thresholding blocks which are commonly added to the total power consumption and area of the analog front-end. The authors in [8] apply compressive sensing on a single-channel pre-recorded EEG data by acquiring measurements in the digital domain. The power saving is significant while the area overhead is not addressed. Due to the youthfulness of the field and the lack of similar electronic architectures that use CS in brain implants, we have compared our results with a Discrete Wavelet Transform (DWT)-based design [49] for intra-cortical implants and several additional systems based on spike/AP detection [37], [47], [48], [50] for implantable neural recording applications. While the design in [49] mainly addresses the area-efficiency of the implantable system and proposes an architecture that sequentially evaluates the DWT of the multichannel data in the digital domain, our results outperform this approach in terms of area and power efficiency.

In addition, high compression ratios are achieved by means of the following thresholding and redundancy removal stages, while the DWT by itself does not result in any data compression. Thresholding, however, results in a significant loss of the signal in non-spiking regions while a more precise recovery is achieved at much lower compression ratios (e.g., at CR=2 in [49]). The chip includes several memory registers containing threshold values of different channels and additional blocks such as controllers, address generator and buffer units which degrade the power and area efficiency of the system.

Some of the reported spike detector systems achieve significant data reduction [37], [47] with negligible overhead in terms of compression power and area [37]. However, the patient-specific threshold setting in such systems can result in design complexity in a real neural interface in addition to the loss of signal in non-spiking regions. Furthermore, the transmitted signal may not be acceptable to the clinicians who usually prefer to have access to the entire iEEG data, even though somewhat lossy, for a thorough neurological examination.

As a final remark, the method presented in this invention can also be implemented in a digital framework, similar to the concept presented in [8], but in a multichannel fashion. By using an ADC per channel and applying the random controlling signals to the digital outputs of channels, which pass through a single digital accumulator block, the full array will be encoded into a digital compressed data. Consequently, any possible advantage of applying CS in the digital domain as expressed in [8] can be exploited in a more area-efficient approach, compared to applying CS per channel. However, the system implemented in this invention benefits from using a single ADC per array which results in a small effective area per channel.

As an alternative approach to the proposed method, implementing an intricate ADC which performs the randomized summation of the channels' outputs will eliminate the summing stage and improve the area efficiency of the multichannel compressive sensing system. Further comparison and characterization of the proposed approaches is required to achieve an optimal model for multichannel signal compression.

The present invention thus relates to a new multichannel architecture and method for compressive recording of biological signals. In particular, a new multichannel architecture and method for compressive recording of cortical signals at the surface of the cortex is proposed. In addition to the area efficiency, the proposed method is easily adaptable to different compression ratios, depending on the sparsity of the input signals. The power efficiency resulting from the compressive sensing methodology in addition to the minimal area cost, make this approach highly relevant for power- and area-constrained multichannel sparse signal acquisition. This approach can be investigated in other applications than neural recording, which require data recording from multiple nodes.

Extensive system-level analysis and simulations confirm the relevance and efficiency of the system for high-density recording applications, compared to alternative compression methods.

Having described now the preferred embodiments of this invention, it will be apparent to one of skill in the art that other embodiments incorporating its concept may be used. This invention should not be limited to the disclosed embodiments, but rather should be limited only by the scope of the appended claims.

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Claims

1. Method for compressing a plurality of biological signals provided by a plurality of measurement devices through a plurality of measuring channels, the method comprising the steps of: forming a multichannel signal matrix XεRd×N from the plurality of biological signals where d is a dimension of the biological signal in each channel and in a time-window and N is the number of channels, R meaning a set of real numbers;obtaining a multichannel measurement vector Y by acquiring M=p/d measurements from each column of the multichannel signal matrix X, to acquire M measurements at each time-window from all channels, where p<<d×N.

2. Method according to claim 1, further including the step of: applying a reshaping operator :Rd×N→Rd·N to the multichannel signal matrix X to transpose said matrix to form a vector of concatenated columns of the multichannel signal matrix X.

3. Method according to claim 2, wherein the multichannel measurement vector Y is obtained by applying a measurement matrix φMC to the vector of concatenated columns of the multichannel signal matrix X.

4. Method according to claim 3, wherein the measurement matrix φMC is represented in matrix form as follows:

5. Method according to claim 4, wherein the multichannel measurement vector Y is determined as follows: Y=φMC(X)

6. Method according to claim 1, further including the step of: recovering a multichannel signal {circumflex over (X)} from the multichannel measurement vector Y using an l1,2 mixed norm as follows:

7. Method according to claim 1, further including the step of: recovering a multichannel neural signal {circumflex over (X)} from the multichannel measurement vector Y using an l1 norm as follows:

8. Implantable sensor including circuitry configured to carry out the method according to claim 1.

9. Implantable system including an implantable transmitter and at least one implantable sensor according to claim 8, the at least one implantable sensor being connected to the implantable transmitter to communicate the compressed signal to the implantable transmitter for transmission to an external receiver.

10. System for compressing a plurality of biological signals and recovering biological signals, the system including the implantable system according to claim 9 and a receiver for receiving a transmitted compressed signal.

11. System according to claim 10, further including a processor configured to receive the compressed signal from the receiver and to process the compressed signal to reconstruct the captured biological signals.

12. Implantable sensor including: a plurality of electrodes for capturing a biological signal,a plurality of amplifiers, each amplifier being connected to a single electrode to amplify the signal captured by each electrode,a random summing circuit for receiving each of the amplified signals, for randomly selecting samples of the amplified captured signals and summing said samples to provide a multichannel measurement signal, anda single analog-to-digital converter for receiving and digitizing the multichannel measurement signal to provide a digital compressed signal.

13. Implantable sensor according to claim 12, wherein each amplifier is a low-noise amplifier including a band-pass transfer function.

14. Implantable sensor according to claim 12, further including a plurality of low-pass filters to limit a high cut-off frequency of the amplified captured signal, each low-pass filter being connected to a single amplifier to receive the amplified captured signal.

15. Implantable sensor according to claim 14, further including a plurality of additional amplifiers, each additional amplifier being connected to a single low-pass filter to amplify the signal provided by said low-pass filter.

16. Implantable sensor according to claim 15, further including a plurality of buffered sample-and-hold circuits, each buffered sample-and-hold circuit being connected to a single additional amplifier to receive the signal amplified by said additional amplifier.

17. Implantable system including an implantable transmitter and at least one implantable sensor according to claim 12, the least one implantable sensor being connected to the implantable transmitter to communicate the compressed signal to the implantable transmitter for transmission to an external receiver.

18. System for compressing a plurality of biological signals and recovering biological signals, the system including the implantable system according to claim 16 and a receiver for receiving a transmitted compressed signal.

19. System according to claim 18, further including a processor configured to receive the compressed signal from the receiver and to process the compressed signal to reconstruct the captured biological signals.