Comparator eliminating need for one's complement logic for signed numbers

Abstract

An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

Description

FIELD OF THE INVENTION

[0001] This invention relates to data processing circuits and systems and more particularly, to digital signal processors, media processors or general purpose microprocessors employing vector or accumulator comparators in the data or instruction paths of digital signal processors, media processors or microprocessors.

BACKGROUND OF THE INVENTION

[0002] There is a continued need in the semiconductor industry to decrease the size of the IC devices. At the same time there is a demand for reducing power consumption while increasing the overall speed of operations. The needs for low power consumption along with reduced device sizes and increased operational speed pose a particular challenge in design of today's comparators.

[0003] The vector and accumulator comparators are usually part of the data paths of digital signal processor (DSP) chips and other similar devices. Comparator operations are directly controlled by the DSP after instructions are issued. Data operation in the comparator macro is conducted at DSP speed, usually in one clock cycle. Therefore, a low power and high speed DSP require low power and high speed data macros. The advent of super scale architecture for vector data path and accumulator data path. A 16-bit vector data path pipe consists of vector multiplier(s), vector adder(s), vector logic, vector shifter(s) and vector comparator macros. The 40 bit accumulator data-path pipe, by comparison, consists of saturating adder(s), accumulator logic and accumulator comparator macros. All data macros receive data simultaneously through the transition register barrier. Therefore, the need of low power and high speed comparators at different points in the data paths pose a challenge.

[0004] In addition, power and silicon areas for the comparator macro becomes significantly larger when the comparator goes from that of a simple integer non-signed use to floating point signed number use and non-signed use. An improved comparator should have the capability of doing both signed and non-signed numbers with the sign control signal telling the comparator macro if the data is signed or non-signed (i.e. The instruction is integer or floating point arithmetic). There is therefore a need for such an improved comparator design that can combine the high speed and low power demands of present semiconductor devices while supporting the decreased overall device sizes.

SUMMARY OF THE INVENTION

[0005] These and other objects are provided by the present invention for an apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is an illustration of a typical block diagram of a comparator performing signed and unsigned number operations as provided in the prior art;

[0007] FIG. 2 is an illustration of a high level block diagram of one embodiment of the present invention;

[0008] FIG. 3 is an illustration of one embodiment of the present invention s provided by FIG. 2;

[0009] FIG. 4 is an illustration of a diagram showing details of an inversion MUX 330, such as that shown in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] FIG. 1, is an illustration of a typical comparator as provided in the prior art. Data inputs are 16 bit numbers VA<0:15> and VB<0:15> as shown at (110) and (120) respectively. If the data is signed the most significant bits VA<0> and VB<0> will indicate the sign of the number. If the data is non-signed the sign control signal will be a “0” and V<0> and VB<0> will be the most significant bit of the number. Note that the non-signed numbers are 16 bits and the signed numbers are actually 15 bits plus the sign bit.

[0011] In FIG. 1, the logical compare of unsigned numbers is performed that portion of the block diagram consisting of the upper comparator logic block (130) which operates on 16 bit data inputs Va<0:15> and Vb<0:15>. This comparator block has two output pins Eq(“1” when Va=Vb) and Lnt (“1” when Va<Vb) as shown at (132) and (134) respectively. These results are then fed into a multiplexer (MUX) as shown at (140) that is controlled by the SIGN bit input, shown as (144). These inputs are then selected and transferred to the MUX output if SIGN=“0” is being performed (i.e. Meaning that a nonsigned comparison is being performed).

[0012] The logical operation of the Result Flag Generator (shown at (170)) is shown in the Table A, below. (Note that the Result Flag Generator block is used in both the prior art solution and the present invention.)

TABLE A
Truth Table for Result Flag Generator
	C Bit,	Equal	0, 0	0, 1	1, 1	1, 0
	A = B,	A < B
	(Eg)	(Lnt)
	0,	0(A > B)	0	0	1	1
	0,	1(A < B)	1	0	1	0
	1,	1	X	X	X	X
	1,	0(A = B)	0	1	0	0

[0013] The signed comparator operation of the prior art solution becomes much more complex in terms of the circuitry required to perform the compare operations. In FIG. 1, Va and Vb are first inverted (2×16=32 inverters) as shown at (150) to produce the “one's complement”. This is followed by an adder shown at (152) that adds a 1 to Va and/or Vb depending on the sign of Va or Vb. The result in turn is then fed into another logical comparator, shown at (160), the same as that used for the unsigned operation. The result of the compare is then fed into a multiplexer (MUX) as shown at (140) and transferred to the output of the MUX if the MUX SIGN control bit is a “1” (meaning signed operation is being performed). The multiplexer output is then provided to the Result Flag Generator (170) which, based on further inputs (C bit and Equal) then outputs a result as indicated in Table A above.

[0014] FIG. 2 is a high level block diagram of one embodiment of the present invention. In this embodiment, a comparator logic shown at (210) and a Result Flag Generator shown at (230) are used in conjunction with a new block referenced to as the Sign Selector and shown at (220). Table B below shows the logic truth table for the Sign Selector. The Sign Selector comprises two new bits Am and Bm. The Am bit is the most significant bit of input A, also indicted as VA<0> (shown at (222)). This bit is the sign of the number if the number is signed. Similarly Bm indicates the sign bit for input VB, also indicated s VB<0> (shown at (224)). A sign feed can also be provided as shown at (223). If AM=“1”, then input VA<0:15> is a positive number. The comparator is in electronic communication with the Sign Selector. In this embodiment, this is accomplished through the Lnt/Ini shown at (213)/(214). The Comparator also feeds the Result Flag Generator through the Eq as shown at (213). The Inout of the Sign Selector shown at 225 is another feed into the Result Flag Generator. These feeds alongside other feeds—when in existence—such as the ones shown at (252) and (254) are combined to create a last result output as shown at (236).

TABLE B
Truth Table for Sign Selector
	Input	Sign	Am	Bm	Ini
	0	x	x	Inout = Ini
	1	0	0	Inout = Ini
	1	0	1	Inout = N-Ini
	1	1	0	Inout = N-Ini
	1	1	1	Inout = Ini
	*Ini: less than
	input
	*N-Ini:
	Negative Ini
	*Inout: less
	than output

[0015] Table C below provides a device comparison table for a “16” bit device which compares the circuit gate count for the embodiment of the present invention as shown in FIG. 2 versus the prior art examples such as the one provided in FIG. 1.

TABLE C
Device Comparison Table for 16 bit Design
	Gate Level	Transistor level
	Design as provided by	126	542
	present invention
	Prior art (traditional)/ design	592	1,920
	Savings (%)	78.72%	71.77%
	*Savings = (T − N)/T

[0016] As provided in Table C, there is substantial improvement due to implementation of the embodiment of FIG. 2 as provided by the present invention.

[0017] FIG. 3 is an embodiment of the present invention showing the Sign Selector of the embodiment provided in FIG. 2 in greater detail. Other embodiments are achievable and the embodiment of FIG. 3 is provided as an example. FIG. 4 illustrates the details of the inversion MUX 330 such as the one shown in FIG. 3. While the invention has been described in accordance with certain preferred embodiments thereof, those skilled in the art will understand the many modifications and enhancements which can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.

Claims

1. In a computing environment, an apparatus for providing high speed computing power while reducing power consumption, comprising: a comparator having at least one comparator input feed; a sign selector in electronic communication with said comparator; said sign selector comprising of at least two sign selector input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of said sign selector input data feeds; a result flag generator in electronic communication with said sign selector and said comparator so that said result flag generator receives a first resultant feed from said comparator and a second resultant feed from said sign selector in order to generate a result output.

2. The apparatus of claim 1, wherein said result flag generator receives other input feeds that are not being supplied to it by said comparator or said sign selector.

3. The apparatus of claim 1, wherein said comparator has at least two comparator input feeds.

4. The apparatus of claim 3, wherein each of said comparator input feeds are at least 16 bits long.

5. The apparatus of claim 1, wherein said sign selector has two sign selector input feeds, respectively identified as a first sign selector input feed and a second sign selector input feed.

6. The apparatus of claim 5, wherein said sign selector input feeds have two dedicated indicators identified receptively as Am and Bm respectively.

7. The apparatus of claim 6, wherein said Am indicator turns on when said first sign selector input feed contains positive numbers.

8. The apparatus of claim 7, wherein said sign selector also comprises a sign feed.

9. The apparatus of claim 1, wherein said sign selector also comprises a sign feed and an Ini feed.

10. The apparatus of claim 10, wherein said input feeds provided to said comparator can be in turn fed to said sign selector through an Ini stream.

11. The apparatus of claim 9, wherein an output from said comparator can be fed to said sign selector through an Ini stream.

12. The apparatus of claim 11, wherein said second resultant input is created by collective operations performed on said Sign, Am, Bm and Ini streams.

13. The apparatus of claim 12, wherein said collective operations are conducted as to create an identical value to that of said Ini stream for said second resultant input when said Sign feed is turned off, regardless of values of Am and Bm; or when said sign feed is turned on, only when said Am and Bm are turned off;

14. The apparatus of claim 12, wherein said collective operations are conducted as to generate said second resultant input to be identical to that of said Ini stream when said sign feed is turned on and said Am and Bm are also both turned on.

15. The apparatus of claim 12, wherein said collective operations are conducted as to generate said second resultant input to be exactly opposite in sign to that of said Ini stream when said sign feed and said Bm are both turned on while said Am is turned off; or when said sign feed and said Am are both turned on while said Bm is turned off.

16. A sign selector for identifying signed numbers from unsigned numbers, comprising: at least two input feeds; a dedicated sign indictor for each input feed respectively identified as Am, Bm, Cm, . . . Zm, . . . an Ini feed and a sign feed; a computator for providing a resultant output feed in a manner that said resultant output feed is generated to be identical to said Ini stream when said sign feed is turned off, regardless of Am, Bm, . . . ; or when said sign feed is turned on but only when said Am, Bm . . . are all turned off.

17. The sign selector of claim 16, wherein there are two input feeds with respective indicators Am and Bm and said resultant output is generated so as to be identical to said Ini stream when said sign feed, Am and Bm are all turned on; and generated to have an opposite sign value to that of said Ini stream when said sign feed and said Bm are both turned on, only when said Am is turned off; or when said sign feed and said Am are both turned on, only when said Bm is turned off.

18. In a computing environment, a method for providing high speed computations while decreasing power consumption, comprising: providing a sign selector unit for differentiating between signed an unsigned numbers; dedicating an equivalent number of indicators for identifying signed numbers from unsigned numbers based on number of input data feeds; providing at least one other data feed to said sign selector via an Ini feed, said Ini feed in turn providing information from a comparator in electronic communication with said sign selector; establishing electronic communication between said sign selector and a result flag generator, said result flag generator also being in electronic communication with said comparator; providing a first resultant stream and a second resultant feed from said comparator and said sign selector respectively to said result flag generator so that a result output can be generated.

19. The method of claim 18, wherein said sign selector also has a sign feed and said at least two other input feeds with sign indicators Am and Bm respectively dedicated to said two other input feeds.

20. The method of claim 19, wherein said second resultant feed's is generated by collective operations performed on said Ini, Am, Bm and sign feeds further comprising the steps of: generating said second resultant input to be identical to said Ini stream when said sign feed is turned off, regardless of values of Am and Bm; generating said second resultant input to be identical to said Ini stream when said sign feed is turned on, only when said Am and Bm are turned off; generating said second resultant input to be identical to said Ini stream when said sign, Am and Bm are all turned on; and generating said second resultant input to be opposite in sign to said Ini stream when said sign feed and said Bm are both turned on, while said Am is turned off; or when said sign feed and said Am are both turned on, while said Bm is turned off.