Comparator

Abstract

A comparator which sets the comparison level depending on the number of transistors used easily ascertains the relative accuracy of the load resistors, is suitable for integration and improves the relative accuracy of input DC biases.

Description

BACKGROUND OF THE INVENTION

This invention relates to a comparator.

A conventional comparator generally has a structure such as that shown in FIG. 3 in which a transistor T.sub.3 is connected in series with a resistor R.sub.3, a transistor T.sub.4 is connected in series with a resistor R.sub.4, the junction of transistor T.sub.3 and resistor R.sub.3 and the junction of transistor T.sub.4 and resistor R.sub.4 are connected to inputs of a differential amplifier A which produces an output corresponding to the difference between the signals supplied to the bases of transistors T.sub.3 and T.sub.4.

In this arrangement, setting a comparison level is performed by changing a reference potential in the case of a single input while it is performed by changing resistors R.sub.3, R.sub.4 in the case of a differential input.

The setting of the comparison level in the case of the differential input will now be described. If the difference between the inputs to the bases of transistors T.sub.3 and T.sub.4 is represented by Vi, and a change in the current is represented by i, currents (I+i), (-i) flow through transistors T.sub.3 and T.sub.4, respectively, and the respective collector potentials V.sub.t1c, V.sub.t2c are given by

V.sub.t1c =V.sub.cc -R.sub.3 (I+i) V.sub.t2c =V.sub.cc -R.sub.4 (i-i)

Since V.sub.t1c =V.sub.t2c, the comparator starts to operate when the comparison level is

i=I(R.sub.4 -R.sub.3)/(R.sub.3 +R.sub.4)

It can be seen from this equation that when, for example, R.sub.3 =R.sub.4, the comparator operates with i=0, while when R.sub.4 =2 R.sub.3, the comparator operates with i=I/3. Namely, when R.sub.4 =2R.sub.3, the comparator operates with application of an operating input voltage v.sub.1 thereto such that a current i=I/3 flows therethrough.

A drawback in the above circuit arrangement is that when the comparison level is set with a reference voltage, the reference voltage and an input potential to be compared must be of high accuracy.

In the case of a differential input, as described above, the comparison level is determined by (R.sub.4 -R.sub.3)/(R.sub.3 +R.sub.4), so that disadvantageously the relative accuracy of the resistors is required. Especially, when the resistances of resistors R.sub.3 and R.sub.4 are different, integration is difficult.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit diagram showing one embodiment of this invention.

FIG. 2 is an electric circuit diagram showing another embodiment.

FIG. 3 is an electric circuit diagram showing a conventional comparator.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, m(m=1, 2 . . . ) transistors T.sub.1 .about.T.sub.1 are connected in parallel and an input terminal a is connected to the respective bases of the transistors. A load resistor R.sub.1 is connected in series with that circuit. Also, n(n=1, 2 . . . but n.noteq.m) transistors T.sub.2 .about.T.sub.2 are connected in parallel and an input terminal b is connected to the respective bases of the transistors. A load resistor R.sub.2 is also connected in series with this circuit. The resistors R.sub.1 and R.sub.2 have the same resistance so as to facilitate integration. The junction of resistor R.sub.1 and transistors T.sub.1.about.T.sub.1 and the junction of resistor R.sub.2 and transistors T.sub.2 .about.T.sub.2 are connected to input terminals of a differential amplifier circuit A.

When a voltage v.sub.i is applied across input terminals a, b, assume that a change current i flows through each transistor and that a bias current (m+n)I flows. A current (I+i.sub.1) flows through each transistor T.sub.1 while a current (I-i.sub.2) flows through each transistor T.sub.2. Since

m(I+i.sub.1)+n(I-i.sub.2)=(m+n)I i.sub.2 =(m/n)i.sub.1 If collector voltages of transistors T.sub.1 and T.sub.2 are shown by V.sub.cm, V.sub.cn, V.sub.cm =V.sub.cc -R m(I+i.sub.1) V.sub.cn =V.sub.cc -R n(I-(m/n)i.sub.1) Since V.sub.cm =V.sub.cn, the comparison level is given by i.sub.1 =(n-m)I/2m As just described, the comparison level is set by the number of transistors T.sub.1 and T.sub.2. For example, when n=2, then comparison is performed with m=1, and i.sub.1 =I/2, and i.sub.2 =I/4.

According to the above arrangement, the load resistors R.sub.1 and R.sub.2 can be arranged to have the same value to set the comparison level. Therefore, the relative accuracy of the load resistors is easy to obtain and the structure is suitable for integration.

Now another embodiment will be described.

In FIG. 2, a first circuit includes m(m=1, 2 . . . ) transistors T.sub.1 .about.T.sub.1 connected in parallel with each other with an input terminal a being connected to the respective bases of the transistors. A first load resistor R.sub.1 is connected in series with this circuit. A second circuit includes n(n=1, 2 . . . , with n.noteq.m) transistors T.sub.2 with an input terminal b being connected to the respective bases of the transistors. A second load resistor R.sub.2 is connected in series with this circuit. The resistors R.sub.1 and R.sub.2 have the same resistance so as to render integration easy. The junction of resistor R.sub.1 and transistor T.sub.1 and the junction of resistor R.sub.2 and transistor T.sub.2 are connected to input terminals of a differential amplifier circuit A. In addition to the above circuit structure, (m-n) transistors T.sub.3 with an input terminal b being connected to the respective bases of the transistors are connected in parallel with resistor R.sub.2 and the second circuit.

When voltage v.sub.i is applied across input terminals a and b, a current (I-i.sub.1) flows through each transistor T.sub.1 and a current (I+i.sub.2) flows through each of transistors T.sub.2 and T.sub.3 where i.sub.1 and i.sub.2 are change currents flowing through transistors T.sub.1 and T.sub.2, respectively, 2mI is the bias current. The following relationship holds from the quality of the operational amplifier circuit

m(I-i.sub.1)+n(I+i.sub.2)+(m-n)(I+i.sub.2) =2mI Therefore, i.sub.2 =i.sub.1. If collector voltages of transistors T.sub.1 and T.sub.2 are shown by V.sub.cm, V.sub.cn, respectively, then V.sub.cm =V.sub.cc =R m(I-i.sub.1) V.sub.cn =V.sub.cc -R n(I+i.sub.1) Since V.sub.cm =V.sub.cn, the comparison level is given by i.sub.1 =(m-n)I/(m+n) In this embodiment, the comparison level is set depending on the number of transistors T.sub.1, T.sub.2 and T.sub.3. For example, when m=2, n=1, the comparison is performed with i.sub.1 =I/3.

According to the above structure, the load resistors R.sub.1 and R.sub.2 can have the same value and the comparison level can be set, so that the relative accuracy of the load resistors is easy to obtain, and the structure is suitable for integration. In addition, the input DC levels can have the same voltage to determine the comparison level, so that the relative accuracy of input DC biases is easy to obtain.

According to this invention, the comparison level can be set depending on the number of transistors used, so that the load resistors can have the same value, the relative accuracy of resistors is easy to obtain and the structure is suitable for integration. Since the input DC biases can have the same voltage, the relative accuracy of biases is improved. In addition, quantities (absolute values) of changes in the collector currents to the input voltages, and bias currents in the respective transistors are the same, so that setting the respective comparison levels is easy.

Claims

1. A comparator comprising:

a first circuit including m(m=1, 2 . . . ) transistors connected in parallel for receiving a first input signal at each respective base of the transistors;

a second circuit including n(n=1, 2 . . . where n.noteq.m) transistors connected in parallel for receiving a second input signal at each respective base of the transistors;

a first load resistor connected in series with the first circuit, and a second load resistor having the same resistance as the first load resistor and connected in series with the second circuit;

said first circuit and said first load resistor constituting a first series-connected circuit, and said second circuit and said second load resistor consituting a second series-connected circuit, said first series-connected circuit and said second series-connected circuit each being connected in parallel with a common power source; and

a differential amplifier having input terminals respectively connected to a junction of the first load resistor and the first circuit and a junction of the second load resistor and the second circuit.

2. The comparator of claim 1; wherein each of said transistors of said first circuit is of the same type connected with the same orientation.

3. The comparator of claim 1; wherein each of said transistors of said second circuit is of the same type connected with the same orientation.

4. The comparator of claim 1; wherein each of said transistors of said first and second circuits is of the same type connected with the same orientation.

5. The comparator of claim 1; wherein each transistor is connected to said differential amplifier.

6. The comparator of claim 1; wherein each transistor of said first circuit is connected to a first terminal of said differential amplifier and each transistor of said second circuit is connected to a second terminal of said differential amplifier.

7. The comparator of claim 6; wherein the collectors of each transistor of said first circuit are connected to said first terminal.

8. The comparator of claim 6; wherein the collectors of each transistor of said second circuit are connected to said second terminal.

9. A comparator comprising:

a first circuit including m(m=2, 3 . . . ) transistors connected in parallel for receiving a first input signal at each respective base of the transistors;

a second circuit including n(n=1, 2 . . . where n<m) transistors connected in parallel for receiving a second input signal at each respective base of the transistors;

a third circuit including (m-n) transistors connected in parallel and receiving the second input signal at each respective base of the transistors;

a first load resistor through which the first circuit is connected to a power source, and a second load resistor having the same resistance as the first load resistor and through which the second circuit is connected to the power source;

said third circuit connected in parallel with a series-connected circuit including the second load resistor and the second circuit; and

a differential amplifier having input terminals respectively connected to a junction of the first load resistor and the first circuit and a junction of the second load resistor and the second circuit.

10. The comparator of claim 9; wherein each of said transistors of said first circuit is of the same type connected with the same orientation.

11. The comparator of claim 9; wherein each of said transistors of said second circuit is of the same type connected with the same orientation.

12. The comparator of claim 9; wherein each of said transistors of said first and second circuits is of the same type connected with the same orientation.

13. The comparator of claim 9; wherein each transistor is connected to said differential amplifier.

14. The comparator of claim 9; wherein each transistor of said first circuit is connected to a first terminal of said differential amplifier and each transistor of said second circuit is connected to a second terminal of said differential amplifier.

15. The comparator of claim 9; wherein the collectors of each transistor of said first circuit are connected to said first terminal.

16. The comparator of claim 9; wherein the collectors of each transistor of said second circuit are connected to said second terminal.