The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2020-0007895, filed on Jan. 21, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the disclosure may generally relate to a comparator which operates at a high speed.
An electronic device including a semiconductor device may perform various internal operations. Whether to perform the internal operations may be determined through a comparator which compares the magnitudes of signals. As the operation of the comparator becomes faster, the speed of the internal operations is improved, which may help the high speed operation of the electronic device.
In an embodiment, a semiconductor device may include a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device may also include a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.
In an embodiment, a semiconductor device may include a selection signal generation circuit configured to generate an (N−1){circumflex over ( )}th bit of a selection signal which has a first logic level, when an N{circumflex over ( )}th bit of a first input signal is different from an N{circumflex over ( )}th bit of a second input signal. The semiconductor device may also include a comparison signal generation circuit configured to output the N{circumflex over ( )}th bit of the first input signal as a comparison signal when the (N−1){circumflex over ( )}th bit of the selection signal has the first logic level, wherein N is a natural number of 2 or more.
In an embodiment, a semiconductor device may include a selection signal generation circuit configured to generate an (N−1){circumflex over ( )}th bit of a selection signal which has a first logic level, when an N{circumflex over ( )}th bit of a first input signal is different from an N{circumflex over ( )}th bit of a second input signal. The semiconductor device may also include a comparison signal generation circuit configured to output a comparison signal by inverting and buffering the N{circumflex over ( )}th bit of the second input signal when the (N−1){circumflex over ( )}th bit of the selection signal has the first logic level, wherein N is a natural number of 2 or more.
The term “preset” means that the numerical value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on an embodiment, the numerical value of a parameter may be set when a process or algorithm starts or may be set during a period during which the process or algorithm is executed.
Terms such as “first” and “second” used to distinguish various components are not limited by components. For example, a first component may be named as a second component, and conversely, the second component may be named as the first component.
When it is described that one component is “coupled” or “connected” to another component, it is to be understood that the one component may be coupled or connected the other component either directly or through an intermediary component. On the other hand, the descriptions of “directly coupled” and “directly connected” should be understood to mean that the one component is coupled and connected to the other component directly without the intervention of another component.
“Logic high level” and “logic low level” are used to describe logic levels of signals. A signal having a “logic high level” is distinguished from a signal having a “logic low level.” For example, when a signal having a first voltage corresponds to a “logic high level,” a signal having a second voltage may correspond to a “logic low level.” Depending on an embodiment, a “logic high level” may be set to a voltage higher than a “logic low level.” Meanwhile, depending on an embodiment, logic levels of signals may be set to different logic levels or opposite logic levels. For example, depending on an embodiment, a signal having a logic high level may be set to have a logic low level, and a signal having a logic low level may be set to have a logic high level.
Hereinafter, various examples of embodiments of the disclosure will be described in detail with reference to the accompanying drawings. These embodiments are only for illustrating the disclosure, and the scope of protection of the disclosure is not limited by these embodiments.
Various embodiments of the present disclosure are directed to a comparator which operates at a high speed. According to some embodiments, through selecting one bit among bits included in input signals, based on selection signals generated by comparing the respective bits included in the input signals, and generating a comparison signal by the selected bit of an input signal, the area and current consumption of a circuit which performs the operation of comparing the input signals may be reduced.
The selection signal generation circuit 100 may generate a selection signal SEL<L−1:1> based on a first input signal IN1<L:2> and a second input signal IN2<L:2>, The selection signal generation circuit 100 may compare a second bit IN1<2> of the first input signal and a second bit IN2<2> of the second input signal, and thereby, may generate a first bit SEL<1> of the selection signal which has a preset logic level determined depending on a comparison result. The selection signal generation circuit 100 may generate the first bit SEL<1> of the selection signal which has a first logic level, when the second bit IN1<2> of the first input signal is different from the second bit IN2<2> of the second input signal, and may generate the first bit SEL<1> of the selection signal which has a second logic level, when the second bit IN1<2> of the first input signal is the same as the second bit IN2<2> of the second input signal. In the present embodiment, the first logic level may be set to a logic low level and the second logic level may be set to a logic high level, but it is to be noted that the embodiment is not limited thereto. The selection signal generation circuit 100 may compare an L{circumflex over ( )}th bit IN1<L> of the first input signal and an L{circumflex over ( )}th bit IN2<L> of the second input signal, and thereby, may generate an (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal which has a preset logic level determined depending on a comparison result. In the present embodiment, the selection signal generation circuit 100 generates the selection signal SEL<L−1:1> by using the first input signal IN1<L:2> and the second input signal IN2<L:2>, but bits of input signals, which are used to generate the selection signal SEL<L−1:1>, are not limited thereto.
The comparison signal generation circuit 110 may generate a comparison signal COM from the first input signal IN1<L:1> or the second input signal IN2<L:1> based on the selection signal SEL<L−1:1>. When the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal which has the first logic level is inputted, the comparison signal generation circuit 110 may output the L{circumflex over ( )}th bit IN1<L> of the first input signal as the comparison signal COM or output the comparison signal COM by inverting and buffering the L{circumflex over ( )}th bit IN2<L> of the second input signal. When the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal which has the second logic level is inputted and an (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal which has the first logic level is inputted, the comparison signal generation circuit 110 may output an (L−1){circumflex over ( )}th bit IN1<L−1> of the first input signal as the comparison signal COM or output the comparison signal COM by inverting and buffering an (L−1){circumflex over ( )}th bit IN2<L−1> of the second input signal. When (L−1){circumflex over ( )}th and (L−2){circumflex over ( )}th bits SEL<L−1:L−2> of the selection signal which have the second logic level are inputted and an (L−3){circumflex over ( )}th bit SEL<L−3> of the selection signal which has the first logic level is inputted, the comparison signal generation circuit 110 may output an (L−2){circumflex over ( )}th bit IN1<L−2> of the first input signal as the comparison signal COM or output the comparison signal COM by inverting and buffering an (L−2){circumflex over ( )}th bit IN2<L−2> of the second input signal. When (L−1){circumflex over ( )}th to second bits SEL<L−1:2> of the selection signal which have the second logic level are inputted and the first bit SEL<1> of the selection signal which has the first logic level is inputted, the comparison signal generation circuit 110 may output the second bit IN1<2> of the first input signal as the comparison signal COM or output the comparison signal COM by inverting and buffering the second bit IN2<2> of the second input signal. When the (L−1){circumflex over ( )}th to first bits SEL<L−1:1> of the selection signal which have the second logic level are inputted, the comparison signal generation circuit 110 may output the comparison signal COM by buffering a first bit IN1<1> of the first input signal or output the comparison signal COM by inverting and buffering a first bit IN2<1> of the second input signal. A logic level of the comparison signal COM may include information on a comparison result of the first input signal IN1<L:1> and the second input signal IN2<L:1>. For example, when the comparison signal COM has the first logic level, it may mean that the first input signal IN1<L:1> is set to be equal to or smaller than the second input signal IN2<L:1>, and when the comparison signal COM has the second logic level, it may mean that the first input signal IN1<L:1> is set to be larger than the second input signal IN2<L:1>. In the present embodiment, the first logic level may be set to a logic low level and the second logic level may be set to a logic high level, but it is to be noted that the embodiment is not limited thereto.
The input signal reception circuit 31 may include inverters IV31 and IV32 and a NAND gate NAND31 which are electrically coupled. The inverter IV31 may invert and buffer the first bit IN2<1> of the second input signal, and may output an output signal. The NAND gate NAND31 and the inverter IV32 may receive the first bit IN1<1> of the first input signal and the output signal of the inverter IV31, perform an AND logic operation, and generate a first pre-code PC<1>.
The first code selection circuit M3(1) may output a second pre-code PC<2> by selecting the second bit IN1<2> of the first input signal or the first pre-code PC<1> based on the first bit SEL<1> of the selection signal. The first code selection circuit M3(1) may output the second bit IN1<2> of the first input signal as the second pre-code PC<2> when the first bit SEL<1> of the selection signal has a logic low level. The first code selection circuit M3(1) may output the first pre-code PC<1> as the second pre-code PC<2> when the first bit SEL<1> of the selection signal has a logic high level.
The second code selection circuit M3(2) may output a third pre-code PC<3> by selecting the third bit IN1<3> of the first input signal or the second pre-code PC<2> based on the second bit SEL<2> of the selection signal. The second code selection circuit M3(2) may output the third bit IN1<3> of the first input signal as the third pre-code PC<3> when the second bit SEL<2> of the selection signal has a logic low level. The second code selection circuit M3(2) may output the second pre-code PC<2> as the third pre-code PC<3> when the second bit SEL<2> of the selection signal has a logic high level.
The (L−2){circumflex over ( )}th code selection circuit M3(L−2) may output an (L−1){circumflex over ( )}th pre-code PC<L−1> by selecting the (L−1){circumflex over ( )}th bit IN1<L−1> of the first input signal or an (L−2){circumflex over ( )}th pre-code PC<L−2> based on the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal. The (L−2){circumflex over ( )}th code selection circuit M3(L−2) may output the (L−1){circumflex over ( )}th bit IN1<L−1> of the first input signal as the (L−1){circumflex over ( )}th pre-code PC<L−1> when the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has a logic low level. The (L−2){circumflex over ( )}th code selection circuit M3(L−2) may output the (L−2)″th pre-code PC<L−2> as the (L−1){circumflex over ( )}th pre-code PC<L−1> when the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has a logic high level.
The (L−1){circumflex over ( )}th code selection circuit M3(L−1) may output the comparison signal COM by selecting the L″th bit IN1<L> of the first input signal or the (L−1){circumflex over ( )}th pre-code PC<L−1> based on the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal. The (L−1){circumflex over ( )}th code selection circuit M3(L−1) may output the L{circumflex over ( )}th bit IN1<L> of the first input signal as the comparison signal COM when the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal has a logic low level. The (L−1){circumflex over ( )}th code selection circuit M3(L−1) may output the (L−1){circumflex over ( )}th pre-code PC<L−1> as the comparison signal COM when the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal has a logic high level.
As illustrated in
As illustrated in
The input signal reception circuit 41 may include inverters IV41 and IV42 and a NAND gate NAND41 which are electrically coupled. The inverter IV41 may invert and buffer the first bit IN2<1> of the second input signal, and may output an output signal. The NAND gate NAND41 and the inverter IV42 may receive the first bit IN1<1> of the first input signal and the output signal of the inverter IV41, perform an AND logic operation, and generate a first pre-code PC<1>.
The first code selection circuit M4(1) may output a second pre-code PC<2> by selecting the second bit IN2<2> of the second input signal or the first pre-code PC<1> based on the first bit SEL<1> of the selection signal. The first code selection circuit M4(1) may output the second bit IN2<2> of the second input signal as the second pre-code PC<2> when the first bit SEL<1> of the selection signal has a logic low level. The first code selection circuit M4(1) may output the first pre-code PC<1> as the second pre-code PC<2> when the first bit SEL<1> of the selection signal has a logic high level.
The second code selection circuit M4(2) may output a third pre-code PC<3> by selecting the third bit IN2<3> of the second input signal or the second pre-code PC<2> based on the second bit SEL<2> of the selection signal. The second code selection circuit M4(2) may output the third bit IN2<3> of the second input signal as the third pre-code PC<3> when the second bit SEL<2> of the selection signal has a logic low level. The second code selection circuit M4(2) may output the second pre-code PC<2> as the third pre-code PC<3> when the second bit SEL<2> of the selection signal has a logic high level.
The (L−2){circumflex over ( )}th code selection circuit M4(L−2) may output an (L−1){circumflex over ( )}th pre-code PC<L−1> by selecting the (L−1){circumflex over ( )}th bit IN2<L−1> of the second input signal or an (L−2){circumflex over ( )}th pre-code PC<L−2> based on the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal. The (L−2){circumflex over ( )}th code selection circuit M4(L−2) may output the (L−1){circumflex over ( )}th bit IN2<L−1> of the second input signal as the (L−1){circumflex over ( )}th pre-code PC<L−1> when the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has a logic low level. The (L−2){circumflex over ( )}th code selection circuit M4(L−2) may output the (L−2){circumflex over ( )}th pre-code PC<L−2> as the (L−1){circumflex over ( )}th pre-code PC<L−1> when the (L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has a logic high level.
The (L−1){circumflex over ( )}th code selection circuit M4(L−1) may output the comparison signal COM by selecting the L{circumflex over ( )}th bit IN2<L> of the second input signal or the (L−1){circumflex over ( )}th pre-code PC<L−1> based on the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal. The (L−1){circumflex over ( )}th code selection circuit M4(L−1) may select and output the L{circumflex over ( )}th bit IN2<L> of the second input signal when the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal has a logic low level. The (L−1){circumflex over ( )}th code selection circuit M4(L−1) may select and output the (L−1){circumflex over ( )}th pre-code PC<L−1> when the (L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal has a logic high level. The inverter IV43 may output the comparison signal COM by inverting and buffering the output signal of the (L−1){circumflex over ( )}th code selection circuit M4(L−1).
As illustrated in
As illustrated in
While various embodiments have been described above, it will be understood by those skilled in the art that the described embodiments represent only a limited number of possible examples. Accordingly, the comparator described herein should not be limited to based on the described embodiments.
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10-2020-0007895 | Jan 2020 | KR | national |
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