Claims
- 1. In a high speed integrated circuit operational amplifier including
- i. an input stage having first and second outputs,
- ii. first and second PNP cascode transistors, an emitter of one of the first PNP cascode transistors being coupled to the first output and an emitter of the other of the first and second PNP cascode transistors being coupled to the second output,
- iii. an NPN transistor having a base electrode coupled to a collector of the first PNP cascode transistor,
- iv. a resistive circuit coupled between a collector of the second PNP cascode transistor and a collector of the NPN transistor, and
- v. a diamond follower output buffer having a first, input coupled to the collector of the second PNP cascode transistor and a second input coupled to the collector of the NPN transistor,
- the improvement comprising in combination:
- (a) a first compensation capacitor coupled between a small signal ground voltage and the collector of the NPN transistor; and
- (b) a second compensation capacitor coupled between the small signal ground voltage and the collector of the second PNP cascode transistor,
- to prevent instability of an output voltage of the diamond follower buffer circuit for high and low levels of the output voltage.
- 2. A high speed integrated circuit operational amplifier comprising in combination:
- (a) an input stage having first and second outputs;
- (b) first and second PNP cascode transistors, an emitter of one of the first PNP cascode transistors being coupled to the first output and an emitter of the other of the first and second PNP cascode transistors being coupled to the second output;
- (c) an NPN transistor having a base electrode coupled to a collector of the first PNP cascode transistor;
- (d) a resistive circuit coupled between a collector of the second PNP cascode transistor and a collector of the NPN transistor;
- (e) a diamond follower output buffer having a first input coupled to the collector of the second PNP cascode transistor and a second input coupled to the collector of the NPN transistor;
- (f) a first compensation capacitor coupled between a small signal ground voltage and the collector of the NPN transistor; and
- (g) a second compensation capacitor coupled between the small signal ground voltage and the collector of the second PNP cascode transistor,
- to prevent instability of an output voltage of the diamond follower buffer circuit for high and low levels of the output voltage.
Parent Case Info
This is a continuation of application Ser. No. 533,000, filed on Sep. 25, 1995.
US Referenced Citations (4)
Continuations (1)
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Number |
Date |
Country |
Parent |
533000 |
Sep 1995 |
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