Compensation for detectors

Abstract

The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Description

BACKGROUND

A logarithmic amplifier (“log amp”) generates an output signal V_OUT that is related to its input signal V_IN by the following transfer function: V_OUT=V_Y log(V_IN/V_Z)   Eq. 1 where V_Y is the slope and V_Z is the intercept. To provide accurate operation, V_Y and V_Z should be stable over the entire operating temperature range of the log amp. In a monolithic implementation of a progressive compression type log amp, temperature compensation of the slope V_Y is typically provided in the gain and detector cells since those are the structures that determine the slope. Temperature stabilization of the intercept V_Z , however, is typically provided at the front or back end of the log amp. For example, a passive attenuator with a loss that is proportional to absolute temperature (PTAT) may be interposed between the signal source and the log amp. Such an arrangement is disclosed in U.S. Pat. No. 4,990,803.

Another technique for temperature compensating the intercept of a log amp involves adding a carefully generated compensation signal to the output so as to cancel the inherent temperature dependency of the intercept. The intercept V_Z of a typical progressive compression log amp is PTAT and can be expressed as a function of temperature T as follows: $\begin{array}{cc}{V}_Z=V_{Z0}\left(\frac{T}{T_0}\right)& \mathrm{Eq}.2\end{array}$ where T₀ is a reference temperature (usually 300° K) and V_Z0 is the value of V_Z at T₀. Substituting Eq. 2 into Eq. 1 provides the following expression: $\begin{array}{cc}{V}_{\mathrm{OUT}}=V_Y\log \left[\left(\frac{V_{\mathrm{IN}}}{V_{Z0}}\right)\left(\frac{T_0}{T}\right)\right]& \mathrm{Eq}.3\end{array}$ which can be rearranged as follows: $\begin{array}{cc}{V}_{\mathrm{OUT}}=V_Y\log \left(\frac{V_{\mathrm{IN}}}{V_{Z0}}\right)-\underset{\mathrm{Temperature}-\mathrm{dependent}}{\underbrace{V_Y\log \left(\frac{T}{T_0}\right)}}& \mathrm{Eq}.4\end{array}$

It has been shown that accurate intercept stabilization can be achieved by adding a correction signal equal to the second, temperature-dependent term in Eq. 4 to the output of a log amp, thereby canceling the temperature dependency. See, e.g., U.S. Pat. No. 4,990,803; and Barrie Gilbert, Monolithic Logarithmic Amplifiers, Aug. 1994, § 5.2.4. A prior art circuit for introducing such a correction signal is described with reference to FIG. 19 in U.S. Pat. No. 4,990,803.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure.

FIG. 2 illustrates an embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.

FIG. 3 illustrates another embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.

FIG. 4 illustrates an embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.

FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure. The embodiment of FIG. 1 includes a temperature compensation circuit 12 that generates a correction signal S_FIX having the form Y log (T/T₀) where Y is a generic slope factor. Since the expression T/T₀ will be used frequently, it will be abbreviated as H=T/T₀ for convenience. The correction signal S_FIX is applied to log amp 10 so as to temperature stabilize the intercept.

The temperature compensation circuit 12 generates the correction signal S_FIX by multiplying a signal having the form H log H by some other factor having a 1/H component. Thus, the H and 1/H cancel, and the only temperature variation in the correction signal is of the form log H. Any suitable scaling my also be applied to obtain the slope factor Y required for the particular log amp being corrected.

FIG. 2 illustrates an embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodiment of FIG. 2, which illustrates one possible technique for implementing the 1/H multiplication shown in FIG. 1, utilizes a transconductance (gm) cell 14. The transfer function of a generic gm cell has a hyperbolic tangent (tanh) form which may be stated a follows: $\begin{array}{cc}{I}_{\mathrm{OUT}}=I_T\tanh \left(\frac{V_i}{V_T}\right)& \mathrm{Eq}.5\end{array}$ where I_T is the bias or “tail” current through the gm cell, V_i is the differential input voltage, and V_T is the thermal voltage which may also be expressed as V_T=V_T0(T/T₀)=V_T0H. If the input signal to the gm cell is kept relatively small, the tanh function may be approximated as simply the operand itself: $\begin{array}{cc}{I}_{\mathrm{OUT}}\approx I_T\frac{V_i}{V_T}& \mathrm{Eq}.6\end{array}$

Now, to implement the generic gm cell in the compensation circuit of FIG. 2, H log H is used as the input V_i to the gm cell, the output current I_OUT is used as the correction signal in the form of a current I_FIX, and V_T0H is substituted for V_T: $\begin{array}{cc}{I}_{\mathrm{FIX}}\approx I_T\frac{H\log H}{V_{T0}H}& \mathrm{Eq}.7\end{array}$ Thus, H and 1/H cancel. If a temperature stable signal (sometimes referred to as a ZTAT signal where the Z stands for zero temperature coefficients) is used for I_T, then I_T/V_T0 is a temperature-stable constant that may be set to any suitable value Y to provide the correct slope. The final form of I_FIX is then given by: I_FIX≈YlogH   Eq. 8 Therefore, the use of a transconductance cell with its inherent 1/H factor provides a simple and effective solution to generating a correction signal having the requisite log H characteristic.

FIG. 3 illustrates another embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodiment of FIG. 3 uses a pair of diode-connected transistors biased by ZTAT and PTAT currents to generate the H log H function, which is then applied to a gm cell in a tightly integrated translinear loop.

Diode-connected transistors Q3 and Q4 are referenced to a positive power supply V_POS, and are biased by currents I_P and I_Z, respectively. I_Z is ZTAT, while I_P is a PTAT current. The base-emitter voltages of Q3 and Q4 are: $\begin{array}{cc}{V}_{\mathrm{BE}3}=V_T\ln \left(\frac{I_P}{I_S}\right)& \mathrm{Eq}.9\\ V_{\mathrm{BE}4}=V_T\ln \left(\frac{I_Z}{I_S}\right)& \mathrm{Eq}.10\end{array}$ and therefore, the ΔV_BE across the bases of Q3 and Q4 is: $\begin{array}{cc}\begin{array}{c}\Delta V_{\mathrm{BE}}=V_{\mathrm{BE}3}-V_{\mathrm{BE}4}=V_T\ln \left(\frac{I_P}{I_S}\right)-V_T\ln \left(\frac{I_Z}{I_S}\right)\\ \Delta V_{\mathrm{BE}}=V_T\ln \left(\frac{I_P}{I_S}\right)\end{array}& \mathrm{Eq}.11\end{array}$ Since I_P can be expressed as I_P=I_ZH, and V_T=V_T0H: $\begin{array}{cc}\Delta V_{\mathrm{BE}}=V_{T0}H\ln \left(\frac{I_{Z}H}{I_Z}\right)\Delta V_{\mathrm{BE}}=V_{T0}H\ln H& \mathrm{Eq}.12\end{array}$ Thus, the ΔV_BE of Q3 and Q4 provide a signal having the form H log H, which is then applied as the input signal V_i to the gm cell.

The gm cell is implemented as a differential pair of emitter-coupled transistors Q1 and Q2 that are biased by a ZTAT tail current I_T. The base-emitter junctions of Q1 and Q2 complete the translinear loop with the base-emitter junctions of Q3 and Q4. The output signal I_OUT from the differential pair is taken as the difference between the collector currents I₁ and I₂ of transistors Q1 and Q2, respectively. Substituting ΔV_BE of Eq. 12 as V_i in Eq. 6 provides: $\begin{array}{cc}{I}_{\mathrm{OUT}}\approx I_T\frac{V_{T0}H\ln H}{V_{T0}H}{I}_{\mathrm{OUT}}\approx I_T\ln H& \mathrm{Eq}.13\end{array}$ By exercising some care in the selection of the scale factor for I_T, the proper slope factor Y may be obtained. Since the output signal I_OUT is in a differential form, it is easy to apply it as the compensation signal I_FIX to the output of any log amp having differential current outputs. This is especially true in the case many progressive compression log amps. I_FIX can simply be connected to the same summing nodes that are used to collect the current outputs from the detector cells for the cascaded gain stages.

FIG. 4 illustrates an embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. In some implementations, the compensation techniques described above may be frequency dependent. That is, although adding a compensation signal of the form Y log H may stabilize the intercept over the entire operating temperature range at a given frequency, a different amount of compensation may be required at different operating frequencies. The embodiment of FIG. 4 provides a terminal 16 that allows a user to vary the amount of compensation depending on the operating frequency.

The example embodiment of FIG. 4 is fabricated on an integrated circuit (IC) chip, preferably including the target log amp to be temperature compensated. A transconductance cell 14, which generates the Y log H correction signal, is biased by a tail current I_T. The tail current is generated by a transistor Q_T which in turn is biased by a voltage V_BIAS. The magnitude of the tail current is determined by the combination of an internal resistor R_INT which is fabricated on the chip, and an external resistor R_EXT, which may be connected through terminal 16. The appropriate value of R_EXT may be provided to the user through a lookup table, equation, etc.

FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. As in the embodiment of FIG. 4, the embodiment of FIG. 5 includes a transconductance cell 14 biased by a tail current I_T generated by transistor Q_T. Rather than setting the tail current directly through an external resistor, however, the current through Q_T is set by an internal resistor R_INT in combination with an operational amplifier (op amp) 18 arranged to drive the base of Q_T in response to an adjustment signal V_ADJ which is applied externally by the user through terminal 16. This eliminates any potential problems with mismatches between internal and external resistors. As an added feature, an on-chip reference voltage V_REF, which is typically available internally on the IC, can be made available to the user through another terminal 20. This enables the user to set the adjustment signal V_ADJ using external divider resistors R1 and R2.

This patent disclosure encompasses numerous inventions relating to temperature compensation of log amps. These inventive principles have independent utility and are independently patentable. In some cases, additional benefits are realized when some of the principles are utilized in various combinations with one another, thus giving rise to yet more patentable inventions. These principles can be realized in countless different embodiments. Only the preferred embodiments have been described. Although some specific details are shown for purposes of illustrating the preferred embodiments, other equally effective arrangements can be devised in accordance with the inventive principles of this patent disclosure.

For example, some transistors have been illustrated as bipolar junction transistors (BJTs), but CMOS and other types of devices may be used as well. Likewise, some signals and mathematical values have been illustrated as voltages or currents, but the inventive principles of this patent disclosure are not limited to these particular signal modes. Also, the inventive principles relating to user-adjustable compensation are not limited to a specific form of temperature compensation, or even to temperature compensation in general. An integrated circuit according to the inventive principles of this patent disclosure may have a user-accessible terminal to adjust the magnitude of any type of compensation, e.g., temperature or frequency, to any type of measurement device.

The embodiments described above can be modified in arrangement and detail without departing from the inventive concepts. Thus, such changes and modifications are considered to fall within the scope of the following claims.

Claims

1. A system comprising: a log amp; and a temperature compensation circuit coupled to the log amp to generate a correction signal by multiplying a signal having the form H log H by a factor 1/H.

2. A system according to claim 1 where the temperature compensation circuit comprises a transconductance cell to multiply the signal having the form H log H by the factor 1/H.

3. A system according to claim 1 where the transconductance cell comprises a tanh function.

4. A system according to claim 1 where the temperature compensation circuit comprises a translinear loop.

5. A system according to claim 1 where the temperature compensation circuit comprises: a pair of junctions arranged to provide the signal having the form H log H; and a transconductance cell coupled to the pair of junctions.

6. A system according to claim 5 where: one of the junctions is biased by a PTAT current; and the other junction is biased by a ZTAT current.

7. A system according to claim 5 where: the log amp is a progressive compression type log amp having a differential structure; and the transconductance cell is coupled to a pair of summing nodes that are used to collect current outputs from detector cells for cascaded gain stages in the log amp.

8. A method comprising: generating a first signal having the form H log H; multiplying the first signal by a factor 1/H, thereby generating a correction signal having the form Y log H; and coupling the correction signal to a log amp.

9. A method according to claim 8 where multiplying the first signal comprises applying the first signal to a transconductance cell.

10. A method according to claim 8 where multiplying the first signal comprises performing a tanh function on the first signal.

11. A method according to claim 8 where the first signal is multiplied in a translinear loop.

12. A method according to claim 8 where generating the first signal comprises: biasing a first junction with a PTAT current; and biasing a second junction with a ZTAT current.

13. A method according to claim 12 further comprising applying the first signal to a transconductance cell.

14. A method according to claim 8 further comprising coupling the correction signal to a pair of summing nodes that are used to collect current outputs from detector cells for cascaded gain stages in a progressive compression log amp.

15. An integrated circuit comprising: a temperature compensation circuit to generate a correction signal having the form Y log H; and a user-accessible terminal to allow a user to externally adjust the magnitude of the correction signal.

16. An integrated circuit according to claim 15 where the temperature compensation circuit is constructed to generate the correction signal by multiplying a signal having the form H log H by a factor 1/H.

17. An integrated circuit according to claim 15 where the temperature compensation circuit is constructed to adjust the magnitude of the correction signal by an external current setting resistor.

18. An integrated circuit according to claim 15 where the temperature compensation circuit comprises a gm cell and a bias transistor in series with the user-accessible terminal.

19. An integrated circuit according to claim 15 where the temperature compensation circuit is constructed to adjust the magnitude of the correction signal in response to a user-provided adjustment signal.

20. An integrated circuit according to claim 19 further comprising a reference signal source coupled to a second user-accessible terminal.

21. An integrated circuit according to claim 15 further comprising a log amp coupled to receive the correction signal.

22. An integrated circuit comprising: a compensation circuit to provide compensation to a measurement device; and a user-accessible terminal to allow a user to externally adjust the magnitude of the compensation.

23. An integrated circuit according to claim 22 where the compensation circuit is to provide temperature compensation.

24. An integrated circuit according to claim 22 where the compensation circuit is to provide frequency compensation.

25. An integrated circuit according to claim 22 further comprising a measurement device coupled to the compensation circuit.