Patent Application
20230031749
Voltage converters convert an input voltage into an output voltage that may be different than the input voltage. Boost converters provide step-up conversion in which the output voltage is greater than the input voltage. Buck converters provide step-down conversion in which the output voltage is less than the input voltage. In both buck and boost converter topologies, an inductor is coupled to a power switch (e.g., a field-effect transistor (FET)). The power FET is turned ON and OFF to store energy in the inductor or transfer energy stored in the inductor to a load coupled to the voltage converter. Adaptive on/off time current control schemes for voltage converters control the switching of the power FET responsive to a comparison of a current through the inductor to a threshold (e.g., a current peak or current valley threshold, based on a compensation ramp provided by a ramp generator) and to a clock signal (e.g., the occurrence of a clock edge).
In an example of the description, a method includes receiving a first indication of an inductor current provided by a voltage converter. The method also includes, responsive to a ratio of a rate of change of the first indication to a rate of change of a compensation ramp being greater than a threshold value, providing a second indication to the ramp generator. The compensation ramp is provided by a ramp generator to control the voltage converter. The second indication is configured to cause the ramp generator to increase an absolute value of the rate of change of the compensation ramp. The method also includes, responsive to the ratio being less than the threshold value, providing a third indication to the ramp generator. The third indication is configured to cause the ramp generator to decrease the absolute value of the rate of change of the compensation ramp.
In another example of the description, a device includes a sample and hold (SH) circuit configured to receive a first indication of an inductor current provided by a voltage converter, and provide a second indication of a rate of change of the first indication. The device also includes an integrator circuit coupled to the SH circuit. The integrator circuit is configured to receive the second indication, and receive a third indication of a rate of change of a compensation ramp. The compensation ramp is provided by a ramp generator to control the voltage converter. Responsive to a ratio of the second indication to the third indication being greater than a threshold value, the integrator circuit is configured to provide a fourth indication to the ramp generator, to cause the ramp generator to increase an absolute value of the rate of change of the compensation ramp. Responsive to the ratio being less than the threshold value, the integrator circuit is configured to provide a fifth indication to the ramp generator, to cause the ramp generator to decrease the absolute value of the rate of change of the compensation ramp.
In yet another example of the description, a device includes a first sample and hold (SH) circuit having a first SH circuit output, and first SH circuit first and second inputs. The first SH circuit first input is adapted to be coupled to an inductor current sense circuit output, and the first SH circuit second input is adapted to be coupled to a timing circuit first output. The device also includes a second SH circuit having a second SH circuit output, and second SH circuit first and second inputs. The second SH circuit first input is coupled to the first SH circuit first input, and the second SH circuit second input is adapted to be coupled to a timing circuit second output. The device also includes a differential amplifier having a differential amplifier output, an inverting input, and a non-inverting input. The inverting input is coupled to the second SH circuit output, and the non-inverting input is coupled to the first SH circuit output. The device also includes a capacitor having a first terminal and a second terminal, where the first terminal is coupled to a ground terminal. The device includes a current source coupled to the second terminal. The device also includes an integrator circuit having an integrator circuit output, and integrator circuit first and second inputs. The integrator circuit first input is coupled to the differential amplifier output, and the integrator circuit second input is coupled to the second terminal. The integrator circuit output is configured to control a slope of a compensation ramp provided by a ramp generator.
As described, control schemes for voltage converters include controlling the switching of the voltage converter (e.g., power FETs of the voltage converter) responsive to a comparison of an inductor current to a threshold (e.g., a current peak or current valley threshold, based on a compensation ramp provided by a ramp generator). For ease of description, a rising slope of the inductor current is indicated as M1, while a falling slope of the inductor current is indicated as M2. A slope of the compensation ramp provided by the ramp generator is indicated as M3. In a voltage converter that is controlled using peak current-mode (PCM) control, maintaining a relationship between M2 and M3 (e.g., a particular ratio) is useful. Similarly, in a voltage controller that is controlled using valley current-mode (VCM) control, maintaining a relationship between M1 and M3 (e.g., a particular ratio) is useful. However, in the PCM control case, M2 varies responsive both to changes in voltage converter input voltage (VIN) and/or output voltage (VOUT), as well as to variances in the value of the inductor. Similarly, in the VCM control case, M1 varies responsive both to changes in VIN and/or VOUT, as well as to variances in the value of the inductor.
To address these problems, examples described below are directed to a slope compensator circuit including a sample and hold (SH) circuit that is configured to receive an indication of the inductor current. In some examples, the indication of the inductor current is a voltage that is proportional to the inductor current, such as a voltage across a sense resistor. The SH circuit is also configured to provide an indication of a rate of change of the inductor current (e.g., an indication of M1 or M2). For example, the SH circuit is configured to sample the inductor current at a first time, and at a second time. In this example, the indication of the rate of change of the inductor current is the difference between the inductor current at the first and second times.
The slope compensator circuit also includes an integrator circuit that is coupled to the SH circuit. The integrator circuit is configured to receive the indication of the rate of change of the inductor current from the SH circuit. The integrator circuit is also configured to receive an indication of a rate of change of the compensation ramp provided by the ramp generator (e.g., an indication of M3). As described below, the ramp generator provides the compensation ramp by charging a capacitor with a current source. In this example, a replica of the current source and capacitor of the ramp generator are coupled to the integrator circuit, and the indication of the rate of change of the compensation ramp is the voltage across the replica capacitor.
The integrator circuit is configured to compare the rate of change of the inductor current (M1 or M2) to the rate of change of the compensation ramp (M3). The integrator circuit is configured to cause the ramp generator to increase an absolute value of the rate of change of the compensation ramp, or M3, responsive to a ratio of M1 or M2 to M3 being greater than a threshold value, which indicates that the rate of change of the compensation ramp is less than specified for a given application (e.g., M3 is shallower relative to M1 or M2 than specified). The integrator circuit is configured to cause the ramp generator to decrease the absolute value of the rate of change of the compensation ramp, or M3, responsive to a ratio of M1 or M2 to M3 being less than the threshold value, which indicates that the rate of change of the compensation ramp is greater than specified for a given application (e.g., M3 is steeper relative to M1 or M2 than specified).
In the example of PCM control, in which M2 is compared to M3, both M2 and M3 are negative values. Accordingly, increasing the absolute value of M3 corresponds to increasing the slope of the compensation ramp in the negative direction, while decreasing the absolute value of M3 corresponds to decreasing the slope of the compensation ramp in the negative direction. In the example of VCM control, in which M1 is compared to M3, both M1 and M3 are positive values. Accordingly, increasing the absolute value of M3 corresponds to increasing the slope of the compensation ramp in the positive direction, while decreasing the absolute value of M3 corresponds to decreasing the slope of the compensation ramp in the positive direction.
The threshold value to which the ratio of M1 or M2 to M3 is compared is determined based on a gain implemented by the slope compensator circuit. In one example, the threshold value is in the range such that M3 is between approximately 0.5*M2 (or M1) and 1.3*M2 (or M1), which is described below. Accordingly, examples of this description vary M3 responsive to variances to M1 or M2, irrespective of whether those variances are due to VIN and/or VOUT changing, due to environmental impacts on component (e.g., inductor) values, or due to manufacturing variances in component (e.g., inductor) values. These and other examples are described below, with reference to the accompanying figures.
The system 100 also includes a control loop 108, which is adapted to be coupled to the load 106, and thus receives VOUT. The control loop 108 is configured to regulate the operation of the voltage converter 102 to provide a VOUT value specified for a given application. In some examples, the control loop 108 includes a beta network 109, which is programmable (e.g., digitally programmable) and specifies or indicates a value to which VOUT is regulated by the control loop 108 and the voltage converter 102. The beta network 109 transforms VOUT into a feedback voltage, labeled VFB in
The system 100 also includes an inductor current sense circuit 112, which is configured to provide an indication of the current through the inductor of the LC filter 104 (e.g., the current having a value iL). In one example, the inductor current sense circuit 112 includes a sense resistor (e.g., having a resistance Ri) coupled to the inductor, and the indication of the inductor current is a voltage across the sense resistor, which is proportional to the inductor current (e.g., iL×Ri).
The indication of the inductor current is provided by the inductor current sense circuit 112 to a slope compensator circuit 114. Generally, the slope compensator circuit 114 (e.g., a slope corrector 115 of the slope compensator circuit 114) determines the rate of change of the inductor current (e.g., M1 or M2) based on the indication of inductor current provided by the inductor current sense circuit 112. The slope compensator circuit 114 also compares M1 or M2 to the rate of change of the compensation ramp (the voltage of which is labeled VRAMP in
The compensation ramp provided by the ramp generator 116 is provided to an inverting terminal of the subtractor 110, such as responsive to PCM control being implemented to control the voltage converter 102. For example, as VRAMP increases (e.g., due to a current source of the ramp generator 116 charging a capacitor of the ramp generator 116), the output of the subtractor 110 (the voltage of which is labeled VSC in
The output of the subtractor 110, as well as the indication of the inductor current from the inductor current sense circuit 112, are provided to a pulse-width modulation (PWM) comparator 118 of the voltage converter 102. The PWM comparator 118 is configured to provide a PWM signal (the voltage of which is labeled VPWM in
In the example of
The integrator circuit 304 also receives an indication of a rate of change of VRAMP (e.g., an indication of M3) that is provided by the ramp generator 116. The integrator circuit 304 is configured to compare the rate of change of the inductor current (M1 or M2) to the rate of change of VRAMP (M3), such as to determine a ratio of M1 or M2 to M3.
The integrator circuit 304 is configured to cause the ramp generator 116 to increase an absolute value of the rate of change of VRAMP, or M3, responsive to a ratio of M1 or M2 to M3 being greater than a threshold value, which indicates that the rate of change of VRAMP is less than specified for a given application (e.g., M3 is shallower relative to M1 or M2 than specified). The integrator circuit 304 is configured to cause the ramp generator 116 to decrease the absolute value of the rate of change of VRAMP, or M3, responsive to a ratio of M1 or M2 to M3 being less than the threshold value, which indicates that the rate of change of VRAMP is greater than specified for a given application (e.g., M3 is steeper relative to M1 or M2 than specified).
As described above, the integrator circuit 304 compares the ratio of M1 or M2 to M3 to a threshold value. This threshold value is determined based on a gain implemented by the slope compensator circuit 114. In one example, such as shown in
The SH circuit 302 of
Each of the first SH circuit 412 and the second SH circuit 414 is configured to sample a voltage provided at the respective first input responsive to a signal edge (e.g., a voltage pulse) being received at the respective second input. The sampled voltage is provided to the output of the respective SH circuit 412, 414, which is “held” at that value until the respective first input is again sampled responsive to a subsequent signal edge being received at the respective second input. The timing circuit 416 is configured to provide a voltage pulse on the S1 output at a first time (t1), and to provide a voltage pulse on the S2 output at a second time (t2) after t1. Accordingly, the SH circuit 302 provides an indication of the rate of change of the inductor 406 current because the first SH circuit 412 samples and provides as its output the inductor 406 current at t1 (e.g., responsive to S1), and the second SH circuit 414 samples and provides as its output the inductor 406 current at t2 (e.g., responsive to S2).
In the example of
The outputs S1, S2 of the timing circuit 416 are also provided as inputs to a set-reset (SR) latch 422. In particular, S1 is provided to the set (S) input of the SR latch 422, while S2 is provided to the reset (R) input of the SR latch 422. Outputs of the SR latch 422 control various switches in the system 400, which are described below.
The system 400 also includes a replica current source 424 and a replica capacitor 426. As described above, the ramp generator 116 provides VRAMP by a current source of the ramp generator 116 charging a capacitor of the ramp generator 116. The replica current source 424 is a replica of the current source implemented in the ramp generator 116, while the replica capacitor 426 is a replica of the capacitor implemented in the ramp generator 116. The replica capacitor 426 is coupled to the replica current source 424 and to a ground terminal. A switch 428 (e.g., a transistor) is also coupled to a node between the replica current source 424 and the replica capacitor 426, and to the ground terminal. The switch 428 is controlled responsive to S1 from the timing circuit 416. For example, the switch 428 is open responsive to S1 being deasserted, and is closed responsive to S1 being asserted. Accordingly, the switch 428 has a control terminal that is adapted to be coupled to the S1 output from the timing circuit 416. The replica capacitor 426 is charged by the replica current source 424 responsive to the switch 428 being open, and is discharged responsive to the switch 428 being closed. The voltage across the replica capacitor 426 (e.g., the voltage at a compensation ramp node between the replica capacitor 426 and the replica current source 424) over time indicates a rate of change of VRAMP provided by the ramp generator 116.
The system 400 also includes switches 430, 432, 434 (e.g., transistors). The switch 430 is coupled to the compensation ramp node (e.g., between the replica capacitor 426 and the replica current source 424) and to an input of the analog integrator circuit 304. The switch 432 is coupled to the output of the differential amplifier 420 and to another input of the analog integrator circuit 304. The switch 434 is coupled to each of the inputs of the analog integrator circuit 304. The switches 430, 432 are controlled responsive to an inverted output (
In the example of
In the example of
In the example of
In another example in which a VCM control scheme is implemented, the timing circuit 416 is configured to provide a voltage pulse on the S1 output responsive to the inductor 406 current increasing, such as following the high-side power FET 402 turning on responsive to the PWM comparator 118 output VPWM being asserted. The timing circuit 416 is configured to then provide a voltage pulse on the S2 output after a period of time has elapsed after providing the voltage pulse on the S1 output. For example, the period of time between time 504 and time 506 is designed to be less than the ON time for the high-side power FET 402, and thus the voltage pulse on the S2 output occurs while the inductor 406 current is still increasing.
Referring to the PCM control example of
At time 506, the timing circuit 416 provides a voltage pulse on the S2 output. Accordingly, the second SH circuit 414 samples the inductor 406 current (e.g., the voltage across the sense resistor 410) and provides the sampled voltage (V) as its output. Also responsive to the voltage pulse on the S2 output, the SR latch 422 is reset (e.g., the
The transconductance amplifier 438 charges or discharges the integrating capacitor 440 with a current proportional to the difference between the inputs to the analog integrator circuit 304. As described above, the analog integrator circuit 304 is configured to compare the rate of change of the falling inductor 406 current (e.g., M2, indicated by P-V and the time between time 504 and time 506) to the rate of change of VRAMP (e.g., M3, indicated by the voltage across replica capacitor 426). The analog integrator circuit 304 is configured to cause the ramp generator 116 to increase an absolute value of the rate of change of VRAMP, or M3, responsive to a ratio of M2 to M3 being greater than a threshold value, which indicates that the rate of change of VRAMP is less than specified for a given application (e.g., M3 is shallower relative to M2 than specified). For example, responsive to the output of the differential amplifier 420 being greater than the voltage across the replica capacitor 426, the transconductance amplifier 438 provides current to the integrating capacitor 440, increasing the voltage across the integrating capacitor 440. Accordingly, the voltage-controlled current source 442 provides an increased current that, in combination with the current from the replica current source 424, is mirrored through current mirror 444 to the ramp generator 116, increasing the slope of VRAMP.
Similarly, the analog integrator circuit 304 is configured to cause the ramp generator 116 to decrease the absolute value of the rate of change of VRAMP, or M3, responsive to a ratio of M2 to M3 being less than the threshold value, which indicates that the rate of change of VRAMP is greater than specified for a given application (e.g., M3 is steeper relative to M2 than specified). For example, responsive to the output of the differential amplifier 420 being less than the voltage across the replica capacitor 426, the transconductance amplifier 438 sinks current from the integrating capacitor 440, decreasing the voltage across the integrating capacitor 440. Accordingly, the voltage-controlled current source 442 provides a decreased current that, in combination with the current from the replica current source 424, is mirrored through current mirror 444 to the ramp generator 116, decreasing the slope of VRAMP.
The particular threshold to which the ratio of M2 (or M1, in the VCM control example) to M3 is compared is dependent on a gain implemented by one or more of the circuit elements of
In another example, the gain implemented by the circuit elements described above is variable responsive to the values of VIN and/or VOUT. In some cases, it is useful to utilize different thresholds (e.g., programmed relationships between M1 (or M2) and M3) for different values of, or relationships between, VIN and VOUT. For example, when VIN and VOUT have a first relationship, it is useful to implement a threshold that results in controlling M3=M2. However, when VIN and VOUT have a second relationship, it is useful to implement a threshold that results in controlling M3=0.65*M2. In one example, a look-up table or other storage mechanism relates values of VIN and VOUT with a corresponding threshold value. The slope compensator circuit 114 is configured to determine, responsive to the values of VIN and VOUT, the associated threshold to be implemented in controlling M3. For example, the slope compensator circuit 114 is configured to implement a first threshold in controlling M3, responsive to the relationship between VIN and VOUT being a first relationship. The slope compensator circuit 114 is configured to implement a second threshold in controlling M3, responsive to the relationship between VIN and VOUT being a second relationship.
In a VCM control example, the functionality of
In the example of
The digital integrator circuit 304 also includes an analog-to-digital converter (ADC) 604, having an input coupled to the subtractor 602 output. The ADC 604 is configured to provide as its output a digital value that corresponds to the ADC 604 input, or the subtractor 602 output. The ADC 604 output is thus a digital value indicative of the comparison between the rate of change of the inductor 406 current and the rate of change of VRAMP.
The digital integrator circuit 304 also includes a digital accumulator 606, having an input coupled to the ADC 604 output. The digital accumulator 606 provides an integrating function in the digital domain, similar to the integrating capacitor 440 in the analog domain, described above. For example, responsive to the output of the ADC 604 being a positive value, the digital accumulator 606 value provided as its output increases. Responsive to the output of the ADC 604 being a negative value, the digital accumulator 606 value provided as its output decreases. A current provided (or sunk) by the digitally-controlled current source 442 is proportional to the digital accumulator 606 value. Accordingly, responsive to the digitally-controlled current source 442 providing current to (or sinking current from) the compensation ramp node, a corresponding current is provided to (or sunk from) the ramp generator 116 to alter the slope of VRAMP provided by the ramp generator 116, as described above.
The method 700 continues in block 704 with comparing a ratio of a rate of change of the first indication (e.g., M2 or M1) to a rate of change of a compensation ramp (e.g., M3) to a threshold value. For example, the first SH circuit 412 and second SH circuit 414 (of the SH circuit 302) provide an indication of the rate of change of the inductor 406 current because the first SH circuit 412 samples and provides as its output the inductor 406 current at t1 (e.g., responsive to S1), and the second SH circuit 414 samples and provides as its output the inductor 406 current at t2 (e.g., responsive to S2). Also, the output of the differential amplifier 420 is an indication of the rate of change of the inductor 406 current when the time period between t1 and t2 is considered. The voltage across the replica capacitor 426 (e.g., the voltage at a compensation ramp node between the replica capacitor 426 and the replica current source 424) over time indicates a rate of change of VRAMP provided by the ramp generator 116.
The particular threshold to which the ratio of M2 (or M1, in the VCM control example) to M3 is compared is dependent on a gain implemented by one or more of the circuit elements of
Responsive to the ratio being greater than the threshold in step 704, the method 700 continues in block 706 with providing a second indication to the ramp generator 116. The second indication causes the ramp generator 116 to increase an absolute value of the rate of change of the compensation ramp. For example, responsive to the output of the differential amplifier 420 being greater than the voltage across the replica capacitor 426, the integrator circuit 304 causes the voltage-controlled current source 442 to provide an increased current that, in combination with the current from the replica current source 424, is mirrored through current mirror 444 to the ramp generator 116, increasing the slope of VRAMP.
Responsive to the ratio being less than the threshold in step 704, the method 700 continues in block 708 with providing a third indication to the ramp generator 116. The third indication causes the ramp generator 116 to decrease the absolute value of the rate of change of the compensation ramp. For example, responsive to the output of the differential amplifier 420 being less than the voltage across the replica capacitor 426, the integrator circuit 304 causes the voltage-controlled current source 442 to provide a decreased current that, in combination with the current from the replica current source 424, is mirrored through current mirror 444 to the ramp generator 116, decreasing the slope of VRAMP.
The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
Uses of the phrase “ground voltage potential” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
