Claims
- 1. A Complementary Metal Oxide Semiconductor (CMOS) transistor device comprising:
a substrate of a first conductivity type; first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type; first and second well regions of respective first and second conductivity formed above respective first and second buried layers; an NMOS transistor and PMOS transistor formed within respective first and second well regions, wherein a buried layer having said NMOS transistor is grounded and said buried layer having said PMOS transistor is biased at a positive supply voltage to improve Single Event Effects occurrence.
- 2. A device according to claim 1, wherein said first conductivity type comprises a P-type conductivity and said second conductivity type comprises an N-type conductivity.
- 3. A device according to claim 1, wherein said first conductivity type comprises an N-type conductivity and said second conductivity type comprises a P-type conductivity.
- 4. A device according to claim 1, and further comprising a buried layer contact well region of second conductivity type formed within said first buried layer, adjacent said well region of first conductivity type having said NMOS transistor, and a body contact engaging said contact well region of first conductivity type.
- 5. A device according to claim 4, and further comprising a local oxidation of silicon structure (LOCOS) separating the contact well region from the well region having said NMOS transistor.
- 6. A device according to claim 1, and further comprising lightly doped drain structures formed within said respective NMOS and PMOS transistors.
- 7. A device according to claim 1, and further comprising a local oxidation of silicon (LOCOS) structure separating said NMOS transistor from said PMOS transistor.
- 8. A device according to claim 1, and further comprising a gate formed of a polysilicon layer, spacer isolation, and gate oxide.
- 9. A device according to claim 1, and further comprising a silicide layer for shorting a source to body in the NMOS or PMOS transistors.
- 10. A device according to claim 1, and further comprising a body tie and buried layer contact area formed within the second well region and contacting the second buried layer for imparting a desired potential thereto.
- 11. Complementary Metal Oxide Semiconductor (CMOS) transistor device comprising:
a P-conductivity substrate; first and second electrically isolated N-conductivity buried layers formed within the substrate; a P-conductivity well region formed above the first N-conductivity buried layer; an NMOS transistor formed within the P-conductivity well region; an N-conductivity well region formed above the second N-conductivity buried layer; a PMOS transistor formed within the N-conductivity well region; and wherein said buried layer having said NMOS transistor is at −V and said buried layer having said PMOS transistor is biased at +V to improve Single Event Effects occurrence.
- 12. A device according to claim 11, wherein said −V is a grounded voltage.
- 13. A device according to claim 11, wherein said +V is a positive voltage.
- 14. A device according to claim 11, and further comprising an N-conductivity buried layer contact well region formed within said first N-conductivity buried layer and adjacent said P-conductivity well region having said NMOS transistor.
- 15. A device according to claim 14, and further comprising a local oxidation of silicon structure (LOCOS) separating the N-conductivity buried layer contact well region from the P-conductivity well region having said NMOS transistor.
- 16. A device according to claim 11, and further comprising lightly doped drain structures formed within said respective NMOS and PMOS transistors.
- 17. A device according to claim 11, and further comprising a local oxidation of silicon (LOCOS) structure separating said NMOS transistor from said PMOS transistor.
- 18. A device according to claim 11, and further comprising a gate formed of a polysilicon layer, spacer isolation, and gate oxide.
- 19. A device according to claim 11, and further comprising a silicide layer for shorting a source to body in the NMOS and PMOS transistors.
- 20. A device according to claim 11, and further comprising an N-conductivity body tie and N-conductivity buried layer contact area formed within the N-conductivity well within the second N-conductivity buried layer and imparting a desired potential thereto.
- 21. A Complementary Metal Oxide Semiconductor (CMOS) transistor device comprising:
a P-conductivity substrate; first and second electrically isolated N-conductivity buried layers formed within the substrate; a P-conductivity well region formed above the first N-conductivity buried layer; an NMOS transistor formed within the P-conductivity well region; an N-conductivity well region formed above the second N-conductivity buried layer; a PMOS transistor formed within the N-conductivity well region; an N-conductivity buried layer contact well region formed within said first N-conductivity buried layer and adjacent said P-conductivity well region having said NMOS transistor; an N-conductivity body tie and N-conductivity buried layer contact area formed within the N-conductivity well within the second N-conductivity buried layer and imparting a desired potential thereto; and wherein said buried layer having said NMOS transistor is at ground and said buried layer having said PMOS transistor is biased at a positive supply voltage to improve Single Event Effects occurrence.
- 22. A device according to claim 21, and further comprising a local oxidation of silicon structure (LOCOS) separating the N-conductivity buried layer contact well region from the P-conductivity well region having said NMOS transistor.
- 23. A device according to claim 21, and further comprising lightly doped drain structures formed within said respective NMOS and PMOS transistors.
- 24. A device according to claim 21, and further comprising a local oxidation of silicon (LOCOS) structure separating said NMOS transistor from said PMOS transistor.
- 25. A device according to claim 21, and further comprising a gate formed of a polysilicon layer, spacer isolation, and gate oxide.
- 26. A device according to claim 21, and further comprising a silicide layer for shorting a source to body in the NMOS or PMOS transistors.
RELATED APPLICATION
[0001] This application is based upon prior filed copending provisional application Ser. No. 60/223,847 filed Aug. 8, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60223847 |
Aug 2000 |
US |