Patent Application
20250208637
Aspects of the present disclosure relate generally to reference circuits, and, more particularly, to complementary to absolute temperature (CTAT) reference circuits.
A reference circuit may be used to generate a reference voltage. The reference voltage may be input to a voltage regulator to provide a circuit with a regulated voltage based on the reference voltage.
The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.
A first aspect relates to a system. The system includes a reference circuit. The reference circuit includes a current source configured to generate a reference current, a resistor, and a programmable diode circuit coupled between the current source and the resistor. The programmable diode circuit includes n-type diodes and first switches, wherein each of the first switches is coupled in series with a respective one of the n-type diodes. The programmable diode circuit also includes p-type diodes and second switches, wherein each of the second switches is coupled in series with a respective one of the p-type diodes.
A second aspect relates to a method for programming a reference circuit. The reference circuit includes a current source, a resistor, and a programmable diode circuit coupled between the current source and the resistor, wherein the programmable diode circuit includes n-type diodes and p-type diodes. The method includes receiving a digital code, enabling a first number of the n-type diodes based on the digital code, and enabling a second number of the p-type diodes based on the digital code.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
The DCO 110 includes an array 120 of tri-state inverters 130-(1,1) to 130-(m, n) arranged in m rows and n columns. Each of the tri-state inverters 130-(1,1) to 130-(m, n) receives a respective control signal C(1,1) to C(m,n) that controls whether the tri-state inverter is turned on or turned off. For example, each of the tri-state inverters 130-(1,1) to 130-(m, n) may be configured to turn on when the respective control signal C(1,1) to C(m,n) is logic one and turn off when the respective control signal C(1,1) to C(m,n) is logic zero, or vice versa. The control signals C(1,1) to C(m,n) may be generated by a digital frequency tuner 160 configured to tune (i.e., adjust) the frequency of the DCO 110 by controlling the number of tri-state inverters 130-(1,1) to 130-(m, n) in the array 120 that are turned on using the control signals C(1,1) to C(m,n), as discussed further below. For ease of illustration, the individual connections between the digital frequency tuner 160 and the tri-state inverters 130-(1,1) to 130-(m, n) are not shown in
In this example, the array 120 has an input 122 coupled to the inputs of the tri-state inverters 130-(1,1) to 130-(m−1) in the first column of the array 120, and an output 124 coupled to the outputs of the tri-state inverters 130-(1,n) to 130-(m,n) in the last column of the array 120. The DCO 110 also includes a loop 126 coupling the output 124 of the array 120 to the input 122 to array 120 to produce oscillations in the DCO 110. The output 115 of the DCO 110 may be coupled to the output 124 of the array 120.
In this example, the signal at the output 115 of the DCO 110 has a frequency approximately equal to ½d, where d is the delay from the input 122 of the array 120 to the output 124 of the array 120. The delay d depends on the number of tri-state inverters 130-(1,1) to 130-(m, n) in the array 120 that are turned on. Thus, the digital frequency tuner 160 can tune (i.e., adjust) the frequency of the DCO 110 by controlling the number of tri-state inverters 130-(1,1) to 130-(m, n) in the array 120 that are turned on using the control signals C(1,1) to C(m,n).
In the example in
In this example, the tri-state inverter 210 turns on when the control signal is one. This is because the second NFET 225 and the second PFET 235 are both turned on when the control signal is one. As a result, the first NFET 220 is coupled to the ground through the second NFET 225, and the first PFET 230 is coupled to the regulated voltage VREG through the second PFET 235. The tri-state inverter 210 turns off when the control signal is zero. This is because the second NFET 225 and the second PFET 235 are both turned off when the control signal is zero. As a result, the first NFET 220 is decoupled from ground, and the first PFET 230 is decoupled to the regulated voltage VREG.
It is to be appreciated that the tri-state inverters 130-(1,1) to 130-(m,n) are not limited to the exemplary implementation shown in
In the example shown in
In this example, the source of the pass transistor 315 is coupled to a supply rail providing the supply voltage Vdd, and the drain of the pass transistor 315 is coupled to the output 312 of the voltage regulator 310, which is coupled to the DCO 110 in this example. The amplifier 320 has a first input 322, a second input 324, and an output 326. The first input 322 is coupled to the output 335 of the reference circuit 330 to receive the reference voltage VREF. The second input 324 is coupled to the output 312 of the voltage regulator 310 via a feedback path 314. Thus, the regulated voltage VREG at the output 312 is fed back to the second input 324 of the amplifier 320. The output 326 of the amplifier 320 is coupled to the gate of the pass transistor 315. Thus, the output 326 of the amplifier 320 provides the gate voltage of the pass transistor 315.
In operation, the amplifier 320 adjusts the gate voltage of the pass transistor 315 in a direction that reduces the difference between the regulated voltage VREG and the reference voltage VREF. This forces the regulated voltage VREG to be approximately equal to the reference voltage VREF. Thus, the regulated voltage VREG may be set to a desired voltage by setting the reference voltage VREF accordingly.
As discussed above, the DCO 110 may be used in a PLL or another type of circuit to provide a tunable frequency. Advantages of the DCO 110 may include a wide tunable frequency range and a small area. However, a challenge with the DCO 110 is that the frequency of the DCO 110 drifts with temperature. For example, the frequency of the DCO 110 may have a positive temperature coefficient in which the frequency increases with rising temperature. This is because an increase in temperature decreases the delays of the tri-state inverters 130-(1,1) to 130-(m,n) for a given regulated voltage VREG, which increases the frequency of the DCO 110.
The frequency drift may be reduced by generating a reference voltage with a negative temperature coefficient that compensates for the positive temperature coefficient of the frequency of the DCO 110. In this regard,
The current source 410 is configured to generate a reference current IREF which flows through the diode circuit 420 and the resistor 450 to generate the CTAT voltage VCTAT. In certain aspects, the current source 410 may be implemented with a temperature compensated-current source or a bandgap reference current source so that the reference current IREF is approximately constant across a temperature range. In the example in shown
In this example, the diode circuit 420 and the resistor 450 are coupled in series between the output 335 of the reference circuit 330 and ground (or some reference potential). In the shown example in
In this example, the diode circuit 420 includes a p-type diode 440 and an n-type diode 430 coupled in parallel. The p-type diode 440 is implemented with a diode-connected p-type field transistor (PFET) in which the drain and gate of the PFET are coupled together. The n-type diode 430 is implemented with a diode-connected n-type field effect transistor (NFET) in which the drain and the gate of the NFET are coupled together. Although one p-type diode 440 and one n-type diode 430 are shown in
The p-type diode 440 has a negative temperature coefficient in which the voltage drop across the p-type diode 440 decreases with increasing temperature for a given reference current IREF. The n-type diode 430 also has a negative temperature coefficient in which the voltage drop across the n-type diode 430 decreases with increasing temperature for a given current IREF. Since the p-type diode 440 and the n-type diode 430 are coupled in parallel, the diode circuit 420 has a negative temperature coefficient in which voltage drop across the diode circuit 420 decreases with increasing temperature for a given current IREF.
In this example, the CTAT voltage VCTAT at the output 335 of the reference circuit 330 is equal to the sum of the voltage drop across the diode circuit 420 and the voltage drop across the resistor 450. Since the voltage drop across the diode circuit 420 decreases with increasing temperature, the CTAT voltage VCTAT also decreases with increasing temperature. The CTAT voltage VCTAT reduces the frequency drift of the DCO 110 with temperature. This is because the CTAT voltage VCTAT decreases the frequency of the DCO 110 with increasing temperature which counteracts the increase in the frequency of the DCO 110 with increasing temperature.
In certain aspects, the resistance of the resistor 450 may be insensitive to temperature over a temperature range so that the resistor 450 has little to no affect on the negative temperature coefficient of the CTAT voltage VCTAT. In this example, the resistance of the resistor 450 may be programmed to set the CTAT voltage VCTAT at a desired voltage at a certain temperature. The diode circuit 420 may then change the voltage of the CTAT voltage VCTAT with temperature to compensate for the positive temperature coefficient of the frequency of the DCO 110 to reduce frequency drift.
The negative temperature coefficient of the diode circuit 420 may be sensitive to process variation, the sizes of the diodes 430 and 440, and/or one or other parameters. This makes it challenging to design the negative temperature coefficient of the diode circuit 420 to match the positive temperature coefficient of the frequency of the DCO 110. Another challenge is that the negative temperature coefficient of the diode circuit 420 may need to be redesigned for different DCOs and/or a redesign of the DCO 110, which increases cost and development time.
To address the above, aspects of the present disclosure provide a programmable diode circuit. In certain aspects, the programmable diode includes n-type diodes and p-type diodes, and switches for programming the number of n-type diodes and/or the number of p-type diodes that are enabled. This allows the negative temperature coefficient of the programmable diode circuit to be programmed (i.e., tuned) by programming the number of n-type diodes and/or the number of p-type diodes that are enabled. For example, the negative temperature coefficient of the diode circuit may be programmed to more closely match the positive temperature coefficient of the DCO frequency for different process corners, different DCO designs, etc.
In this example, the programmable diode circuit 510 includes n-type diodes 525-1 to 525-n and p-type diodes 545-1 to 545-n. In the example shown in
The programmable diode circuit 510 also includes first switches 530-1 to 530-n configured to control a number of the n-type diodes 525-1 to 525-n that are enabled. In the example shown in
In the example shown in
In the example shown in
The programmable diode circuit 510 also includes second switches 550-1 to 550-n configured to control a number of the p-type diodes 545-1 to 545-n that are enabled. In the example shown in
In the example shown in
Thus, the number of the n-type diodes 525-1 to 525-n that are enabled and the number of the p-type diodes 545-1 to 545-n that are enabled can be programmed using the control signals n_en<0> to n_en<n−1> and p_en<0> to p_en<n−1>, respectively. It is to be appreciated that, in some implementations, the number of the n-type diodes 525-1 to 525-n that are enabled and the number of the p-type diodes 545-1 to 545-n that are enabled may be different (e.g., to adjust the ratio of p-type diodes that are enabled to n-type diodes that are enabled). The number of the n-type diodes 525-1 to 525-n that are enabled may also be referred to as a first number, and the number of the p-type diodes 545-1 to 545-n that are enabled may be referred to as a second number. The first number and the second number may be equal or may be different.
In this example, the negative temperature coefficient of the programmable diode circuit 510 can be programmed (i.e., tuned) by programming the number of the n-type diodes 525-1 to 525-n that are enabled and the number of the p-type diodes 545-1 to 545-n that are enabled using the control signals n_en<0> to n_en<n−1> and p_en<0> to p_en<n−1>, respectively. For example, the negative temperature coefficient of the programmable diode circuit 510 may be programmed to more closely match the positive temperature coefficient of the frequency of the DCO 110 (shown in
In this example, each of the first transistor 820 and the second transistor 822 is coupled between a supply rail 812 and the output 335 of the reference circuit 330. The gate of the first transistor 820 is coupled to the CTAT circuit 815, and the gate of the second transistor 822 is coupled to the PTAT circuit 810. Each of the first transistor 820 and the second transistor 822 may be implemented with a respective PFET, as shown in the example in
The PTAT circuit 810 is configured to generate a PTAT current and mirror the PTAT current to the second transistor 822. Thus, the current IPTAT flowing through the second transistor 822 is proportional to the PTAT current generated by the PTAT circuit 810. As used herein, “proportional” covers the possibility of a proportionality factor of one. The CTAT circuit 815 is configured to generate a CTAT current and mirror the CTAT current to the first transistor 820. Thus, the current ICTAT flowing through the first transistor 820 is proportional to the CTAT current generated by the CTAT circuit 815. The current ICTAT flowing through the first transistor 820 and the current IPTAT flowing through the second transistor 822 are combined into the reference current IREF, which flows through the diode circuit 510 and the resistor 450. The reference current IREF is approximately constant over a temperature range when the negative temperature coefficient of the current ICTAT and the positive temperature coefficient of the current IPTAT are matched over the temperature range.
In the example in
The current mirror 845 is configured to mirror the current flowing through the resistor 834 to the second transistor 822. As discussed further below, the current flowing through the resistor 834 provides the PTAT current. The current mirror 845 may also be configured to provide approximately equal currents for the third transistor 830 and fourth transistor 832.
In operation, the third transistor 830 and the fourth transistor 832 are operated in the subthreshold region. The voltage drop across the resistor 834 is equal to the difference of the gate-to-source voltage of the third transistor 830 and the gate-to-source voltage of the fourth transistor 832. The voltage difference has a positive temperature coefficient, causing the current flowing through the resistor 834 to also have a positive temperature coefficient. The current flowing through the resistor 834 provides the PTAT current discussed above. The current mirror 845 mirrors the PTAT current flowing through the resistor 834 to the second transistor 822 to provide the current IPTAT.
In the example in
The drain of the eighth transistor 858 is coupled to the drain of the seventh transistor 856 and the gate of the eighth transistor 858, the gate of the eighth transistor 858 is coupled to the gate of the ninth transistor 860, the source of the eighth transistor 858 is coupled to the low rail 814, and the source of the ninth transistor 860 is coupled to the low rail 814.
The gate of the tenth transistor 840 is coupled to the gate of the second transistor 822 to mirror the PTAT current generated by the PTAT circuit 810 to the second transistor 822. The source of the tenth transistor 840 is coupled to the supply rail 812, the drain of the tenth transistor 840 is coupled to the drain of the ninth transistor 860, and a capacitor 842 is coupled between the gate and the drain of the tenth transistor 840.
In operation, the sixth transistor 854 mirrors the PTAT current flowing through the resistor 834 to the seventh transistor 856. The current flowing through the seventh transistor 856 flows through the eighth transistor 858, which mirrors the current to the ninth transistor 860. The current flowing through the ninth transistor 860 then flows through the tenth transistor 840, which mirrors the current to the second transistor 822.
The CTAT circuit 815 includes an eleventh transistor 862, a twelfth transistor 866, a thirteenth transistor 864, a fourteenth transistor 872, a fifteenth transistor 874, a resistor 868, and a capacitor 870.
The gate of the eleventh transistor 862 is coupled to the gate of the tenth transistor 840, and the source of the eleventh transistor 862 is coupled to the supply rail 812. The drain of the twelfth transistor 866 is coupled to the drain of the eleventh transistor 862, the source of the twelfth transistor 866 is coupled to the low rail 814, and the resistor 868 is coupled to between the gate of the twelfth transistor 866 and the low rail 814. The gate of the fourteenth transistor 872 is coupled to the drain of the twelfth transistor 866, and the source of the fourteenth transistor 872 is coupled to the low rail 814. The capacitor 870 is coupled between the gate of the fourteenth transistor 872 and the low rail 814. The sources of the thirteenth transistor 864 and the fifteenth transistor 874 are coupled to the supply rail 812, and the gate of the fifteenth transistor 874 is coupled to the gate of the thirteenth transistor 864, the gate of the first transistor 820, and the drain of the fifteenth transistor 874. The drain of the thirteenth transistor 864 is coupled to the gate of the twelfth transistor 866, and the drain of the fifteenth transistor 874 is coupled to the drain of the fourteenth transistor 872.
In operation, the PTAT current from the PTAT circuit 810 is mirrored to the eleventh transistor 862. The current flowing through the eleventh transistor 862 flows through the twelfth transistor 866, which is operated in the subthreshold region. The gate-to-source voltage of the twelfth transistor 866 (which has a negative temperature coefficient) appears across the resistor 868. This causes the current flowing through the resistor 868 to have a negative temperature coefficient, which provides the CTAT current discussed above. The thirteenth transistor 864 mirrors the CTAT current flowing through the resistor 868 to the first transistor 820.
In certain aspects, switches may be coupled to the reference current source 410 to power down the reference current source 410 when the reference current source 410 is not needed to conserve power. In this regard,
The power switch 910 is coupled between a second supply rail 912 and the supply rail 812 of the reference current source 410. In the discussion below, the supply rail 812 is referred to as the first supply rail. The second supply rail 912 provides a supply voltage Vdd. When the power switch 910 is turned on, the first supply rail 812 is coupled to the second supply rail 912. As a result, the supply voltage Vdd is provided to the first supply rail 812 (also referred to as an internal supply rail). When the power switch 910 is turned off, the first supply rail 812 is decoupled from the second supply rail 912.
Each of the pull-down switches 920, 930, 940, 950, and 960 is coupled between a respective internal node of the reference current source 410 and the low rail 814 (e.g., ground potential). In the example shown in
In this example, the on/off states of the power switch 910 and the pull-down switches 920, 930, 940, 950, and 960 are controlled by the power control signal pdn. For example, the power switch 910 may turn off and the pull-down switches 920, 930, 940, 950, and 960 may turn on when the power control signal pdn has a first logic value (e.g., one). The power switch 910 may turn on and the pull-down switches 920, 930, 940, 950, and 960 may turn off when the power control signal pdn has a second logic value (e.g., zero).
In this example, the power control signal pdn may be set to the first logic value to power down the reference current source 410. In this case, the first supply rail 812 is decoupled from the second supply rail 912, and each of the pull-down switches 920, 930, 940, 950, and 960 pulls down the respective internal node of the reference current source 410 to the low rail 814 (e.g., ground potential).
The power control signal pdn may be set to the second logic value to power up the reference current source 410. In this case, the first supply rail 812 is coupled to the second supply rail 912 through the power switch 910, and each of the pull-down switches 920, 930, 940, 950, and 960 is turned off.
It is desirable to shorten the start up time of the reference circuit 330. In this regard,
In this example, a delay circuit 1010 is coupled between the power switch 910 and the first pull-down switch 920. The delay circuit 1010 delays the power control signal pdn and outputs the delayed power control signal pdn_dly to the first pull-down switch 920. In the example in
During power up, the power control signal pdn transitions from the first logic value (e.g., one) to the second logic value (e.g., zero). When the power control signal pdn transitions to the second logic value, the power switch 910 turns on, coupling the first supply rail 812 to the second supply rail 912. When the power switch 910 initially turns on, the first pull-down switch 920 remains turned on for a short period of time equal to the delay of the delay circuit 1010 since the first pull-down switch 920 receives the delayed power control signal pnd_dly. As a result, the gate of the tenth transistor 840 in the current mirror 845 is pulled down to the low rail 814 by the first pull-down switch 920 for the short period of time. Since the tenth transistor 840 is implemented with a PFET in this example, the tenth transistor 840 is turned on. This causes a strong current to flow through the tenth transistor 840, which decreases the start-up time.
Although the first pull-down switch 920 is coupled between the gate of the tenth transistor 840 in the example shown in
At block 1110, a digital code is received. For example, the digital code may correspond to the digital code ctat_ctrl<k:0>.
At block 1120, a first number of the n-type diodes are enabled based on the digital code. For example, the controller 610 may enable the first number of the n-type diodes. The first number may be less than or equal to the total number of n-type diodes in the programmable diode circuit.
At block 1130, a second number of the p-type diodes are enabled based on the digital code. For example, the controller 610 may enable the second number of the p-type diodes. The second number may be less than or equal to the total number of p-type diodes in the programmable diode circuit. The first number and the second number may be different.
Implementation examples are described in the following numbered clauses:
Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical coupling between two structures. It is also to be appreciated that the term “ground” may refer to a direct current (DC) ground or an alternating current (AC) ground, and thus the term “ground” covers both possibilities. An AC ground may be provided by a DC voltage. As used herein, the term “approximately” means within 90 percent to 110 percent of the stated value. It is to be appreciated that a transistor may be implemented on a chip with two or more transistors coupled in parallel and/or series.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
