A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram illustrating a flash memory of the prior art; and
FIG. 2 is a schematic diagram illustrating a preferred embodiment of the present invention.
Claims
1. A complex memory chip, comprising:
a first pin being configured to transmit a first voltage;a second pin being configured to transmit a second voltage lower than the first voltage, so as to define a working voltage in association with the first voltage;a voltage generator for generating a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage;a flash memory for erasing a data according to the third voltage; anda static random access memory (SRAM);wherein the flash memory and the SRAM are operated under the working voltage.
2. The complex memory chip of claim 1, wherein the voltage generator is disposed in the flash memory.
3. The complex memory chip of claim 1, further comprising an address pin, wherein the flash memory and the SRAM transmit an address signal via the address pin.
4. The complex memory chip of claim 3, wherein the address signal is one of an address signal of the flash memory and an address signal of the SRAM.
5. The complex memory chip of claim 1, further comprising a data pin, wherein the flash memory and the SRAM transmit a data signal via the data pin.
6. The complex memory chip of claim 5, wherein the data signal is one of a data signal of the flash memory and a data signal of the SRAM.
7. The complex memory chip of claim 5, wherein the flash memory has an operation status signal which is transmitted via the data pin.
8. The complex memory chip of claim 7, wherein the operation status signal is one of a reading status signal, a writing status signal, and a data erasing status signal.
9. The complex memory chip of claim 1, further comprising a control signal pin, wherein the flash memory and the SRAM transmit a control signal via the control signal pin.
10. The complex memory chip of claim 9, wherein the control signal pin is one of an output-enabling pin and a write-enabling pin.
11. A complex memory chip, comprising:
a first pin being configured to transmit a first voltage;a second pin being configured to transmit a second voltage lower than the first voltage, so as to define a working voltage in association with the first voltage;a data pin;a flash memory for transmitting an operation status signal via the data pin; andan SRAM;wherein the flash memory and the SRAM are operated under the working voltage and transmit a data signal via the data pin.
12. The complex memory chip of claim 11, wherein the data signal is one of a data signal of the flash memory and a data signal of the SRAM.
13. The complex memory chip of claim 11, wherein the operation status signal of the flash memory is one of a reading status signal, a writing status signal, and a data erasing status signal.
14. The complex memory chip of claim 11, further comprising an address pin, wherein the flash memory and the SRAM transmit an address signal via the address pin.
15. The complex memory chip of claim 14, wherein the address signal is one of an address signal of the flash memory and an address signal of the SRAM
16. The complex memory chip of claim 11, further comprising a control signal pin, wherein the flash memory and the SRAM transmit a control signal via the control signal pin.
17. The complex memory chip of claim 16, wherein the control signal pin is one of an output-enabling pin and a write-enabling pin.
Patent Application
20070223274
