Patent Grant
10490322
This application is a U.S. National Stage of International Application No. PCT/EP2017/050409, filed Jan. 10, 2017, which claims the benefit of German Patent Application No. 102016100352.2, filed Jan. 11, 2016, both of which are incorporated herein by reference in their entireties.
The application relates to a component carrier having a built-in ESD protective function, which can be equipped with electrical components and in this case provides ESD protection for said components, and to a method for producing same.
Varistors can be used for protecting sensitive installations, components and networks against ESD (electrostatic discharge). Varistors are nonlinear components whose resistance decreases greatly when a specific applied voltage is exceeded. Varistors are therefore suitable for harmlessly dissipating overvoltage pulses. Varistors are produced from a zinc oxide ceramic having a grain structure.
Varistors can be integrated poorly in modular ceramics and are therefore usually used as discrete components.
Discrete components having a varistor function or generally having an ESD protective function are directly soldered onto a ceramic substrate, a leadframe, a circuit board or a printed circuit board and electrically connected to the component to be protected.
It is also possible to integrate such protection elements into a laminate during the production thereof.
Furthermore, it is possible to position the protection element in a cutout of the substrate, of the carrier plate or of the laminate such that it is adjacent to other electrically conductive structures provided for connection to further components. Although this results in a small component height, it requires sufficient placement area.
It is also possible to use a varistor ceramic as a component substrate and to integrate the protective function into the substrate.
It is an object of the present invention to further improve the integration of a protective function or of a protection element into a component carrier and in particular to provide a component carrier of smaller design. A further partial object consists in specifying a main body having a protective function and an improved thermal conductivity.
This object is achieved by means of a component carrier having the features of claim 1. Advantageous configurations of the invention and also a method for producing a component carrier can be gathered from further claims.
The component carrier comprises a ceramic main body having electrical terminal pads on a first surface and a first electrode pair on a second surface. Electrical terminal pads and first electrode pair are electrically connected to one another via plated-through holes. A varistor layer is applied above the first electrode pair. Furthermore, a second electrode pair is applied above the varistor layer and electrically connected in parallel with the first electrode pair. First and second electrode pairs together with the varistor layer arranged therebetween form a varistor and thus, in the case of an overvoltage present at the terminal pads or generally in the case of an ESD pulse, can dissipate the latter harmlessly by way of a short circuit through the varistor layer, with the result that a component mounted onto the second electrode pair or electrically connected to the second electrode pair is not damaged.
The varistor layer abuts flat on the main body, can utilize the first electrode pair thereof as a varistor electrode and therefore takes up only little additional volume. The component carrier therefore has a relatively small volume.
In this case, the varistor layer is laterally dimensioned such that it is circumferentially spaced apart from the edges of the component carrier. This has the advantage that no side edge of the varistor layer terminates at a side surface of the component carrier. As a result, the varistor layer, after the mounting of the component, is protected against mechanical and other influences.
Such a lateral structuring of the varistor layer has the advantage in particular during the structuring of the main body, or during the singulation of individual component carriers along separating lines, that the separating lines are located outside the varistor layer, with the result that the latter need not be severed during singulation and therefore cannot actually be damaged in the process.
The second electrode pair preferably comprises a solderable material or is provided with a solderable surface layer. An electrical component can then be directly soldered onto the varistor layer or the second “upper” electrode pair thereof. It is not necessary to provide additional terminal pads for such a component. Moreover, the varistor is mechanically protected between component and main body. For the varistor, therefore, a protective layer or a passivation either is not necessary at all or can be produced in a simple and cost-effective embodiment.
The component carrier is suitable for components which generate heat loss during operation. Said heat loss can be dissipated from the component via the component carrier. In this case, the main body advantageously comprises aluminum nitride. The latter is distinguished by a particularly good thermal conductivity. In the case of heat-generating components, this advantage can compensate for the disadvantage of the higher material price. However, other ceramic materials are also suitable for the main body, for example aluminum oxide, silicon carbide, boron nitride or others.
The heat dissipation can also be improved by means of other measures. In this regard, the component carrier can be provided with thermal vias that improve the heat transfer through the main body. The thermal vias are preferably connected to a heat sink that can be provided for example on a circuit board onto which the component carrier is bonded.
In one embodiment, at least the second electrode pair comprises a copper-containing material. In order to produce the electrode pair, copper-containing and silver-containing electrode pastes can be printed which with additional finish yield a solderable surface. However, other electrode pastes are also known onto which soldering can already be effected directly without additional finish.
In one embodiment, at least one internal electrode is arranged between first and second electrode pairs, said at least one internal electrode being embedded into the varistor layer in an electrically floating fashion or being electrically connected to a respective electrode of the first electrode pair. This has the advantage during production that a greater tolerance is acceptable since, even with poorer mutual geometric orientation, all that changes is the volume of the active varistor region and thus the capacitance thereof. What matters for the magnitude of the varistor voltage is the smallest distance between the electrodes and thus the smallest number of transitions through which harmful overvoltages are dissipated harmlessly as a short circuit within the varistor. A higher volume leads to a higher current endurance, such that higher currents can thus be dissipated.
A floating internal electrode has the advantage of voltage division, such that the voltage present between an electrode pair and the internal electrode is halved as a result. The varistor voltage at which the current dissipation via the varistor commences is then correspondingly lower and can be obtained with correspondingly thinner varistor layers. An electrically connected internal electrode enlarges the varistor area and thus improves the current dissipation in the case of an overvoltage or an ESD pulse.
In a further embodiment, a passivation layer is arranged above the varistor layer and the second electrode pair such that the varistor layer is enclosed on all sides and completely between main body, second electrode pair and passivation layer and only terminal contacts remain free of and not covered by the second electrode pair. The passivation layer can be applied and structured after the varistor layer has been applied. The second electrode pair can then be produced in surface regions that are free of the passivation layer.
It is also possible to produce the passivation layer after the second electrode pair has been produced. Terminal contacts for the mounting of the component can then be produced in surface regions that are free of the passivation layer.
A method according to the invention for producing a component carrier comprises the following steps:
Method steps a) to d) can substantially follow corresponding known methods without modification.
In step e), the varistor layer is then used as a green film. This can be effected before or after the firing of the printed first electrode pair. The electrode paste thereof can comprise glass components for better adhesion and thus simultaneously also serve as an adhesion promoter for the varistor layer.
The green film for the varistor layer can be laminated onto the main body over the whole area. In this case, the main body can be a ceramic wafer on which a multiplicity of individual carriers can be produced and processed to completion in parallel before the wafer is then singulated into the individual carriers.
If the varistor is embodied with an internal electrode, the latter can be applied on the green film before laminating. However, a mutual orientation between the varistor layer with the internal electrode and the main body with the first electrode pair is then necessary. This is obviated when the the internal electrode is produced after laminating. It is possible, but not necessary, to fire or to sinter individual or more layers after laminating or printing before the next layer is applied.
It is also possible, however, to fabricate a separate prelaminate from at least two or more varistor layers/green films and the at least one internal electrode embedded therein, which prelaminate indeed already has the required cohesion of the layers/films, but itself is also still laminatable or can be laminated onto the main body.
In all cases, the laminated green film is structured such that a circumferential marginal region of the second surface of the main body is also exposed besides an access to the first electrode pair. The structuring can be carried out rapidly and structurally accurately using a laser.
The metallizations of the component carrier such as terminal pads, first and second electrode pairs can be produced by printing a paste containing Cu and glass portions, which has a solderable surface after firing. A paste containing only Cu as metal besides glass components can be provided with a finishing coating, a so-called finish, and thus with a solderable surface. Such a finish can contain Ni, Au, Pt, Pd or Sn.
The internal electrode can be printed just like the other metallizations. This can be effected on an already laminated green film with varistor material or on the separate, not yet laminated green film. A green film provided with an internal electrode can also be printed over the whole area on a large-area main body and not be structured until later. In this case, the internal electrode is oriented toward the first electrode pair. The orientation is less critical if the internal electrode is electrically floating. If the at least one internal electrode is connected to an electrode, then the orientation of the internal electrode toward the first electrode pair has to be effected with lower tolerance. In that case the structuring of the green film should also be carried out such that the internal electrodes to be interconnected with identical polarity are cut at a respective structure edge of the green film or of the green film stack and can be connected to the second electrode pair later.
After laminating the green film, before or after printing the second electrode pair, a passivation layer can be applied and structured such that in the first case only the surface region provided for the second electrode pair remains free of the passivation layer. In the second case the printed second electrode pair remains free of the passivation layer only in such a region in which solderable terminal contacts are subsequently produced by reinforcement of the second electrode pair.
The passivation layer can comprise a glass, ceramic or other dielectric oxides, nitrides, carbides or a polymer such as e.g. polyimide. A polymer can be selected such that it withstands further method steps such as e.g. electroplating, the firing of printed metallizations or soldering processes.
The passivation layer is usually provided to remain on the component carrier even when the latter is equipped with a component and, for its part, incorporated into a circuit environment such as e.g. a circuit board.
The solderable terminal contacts are produced by electrodeposition of the second electrode pair on the exposed region thereof. This reinforcement can simultaneously constitute a solderable metal layer.
It is possible, as stated, for a large-area main body to be provided and singulated later into a multiplicity of component carriers. The separation of the main body is effected exclusively in the marginal region and thus at a distance from the respective edge of the varistor layer. The singulation can be effected in a simple manner e.g. by sawing.
The component carrier according to the invention and various method variants for producing it are explained in greater detail below on the basis of exemplary embodiments and with reference to the associated figures. The figures show schematic cross sections and are not drawn as true to scale. Individual parts may be illustrated in an enlarged manner in order to afford better understanding.
A varistor layer VS bears above both electrodes of the first electrode pair EP1. A second electrode pair EP2 is fitted above the varistor layer VS and structured such that a first electrode of the second electrode pair is in contact with a first electrode of the first electrode pair. Correspondingly, the second electrode of the second electrode pair EP2 is in contact with the second electrode of the first electrode pair EP1.
In this case, an electrode of the first electrode pair overlaps an electrode of the second electrode pair EP2 such that with the intervening varistor layer VS in the overlap region a varistor arises.
A part of the active varistor is illustrated as an excerpt in an enlarged view above the component carrier BT. Close-packed zinc oxide grains ZK are arranged in the varistor layer VS. As soon as the voltage present at first and second electrode pairs EP1, EP2 exceeds the breakdown voltage, a conductive path forms between individual zinc oxide grains ZK, with the result that the varistor layer VS becomes conducting and the current is dissipated harmlessly by way of a short circuit through the varistor layer via both electrodes.
The term varistor voltage denotes the voltage drop across the varistor given an impressed current of 1 mA. It does not have special electro-physical importance, but is used as a practical, standardized reference point for specifying varistors.
The main body GK is preferably formed from aluminum oxide or, for better heat conduction, from aluminum nitride. Other ceramic materials, too, are theoretically suitable, but costly. Terminal pads and first electrode pair comprise a fired conductive paste, for example based on silver. The same correspondingly applies to the plated-through hole DK. The second electrode pair EP2, too, is preferably formed from a conductive fired paste and either is already solderable per se or is provided with a solderable surface. A copper-containing paste which either already has a solderable surface per se by virtue of additives or has a solderable surface finish can be used in a cost-effective manner.
In the next step, a green film of a varistor layer VS is laminated onto the second surface above the first electrode pair EP1. This is carried out over the whole area over the entire surface of the main body GK.
In the next step, the whole-area varistor layer VS is structured with the aid of a structuring tool ST. In this case, the varistor layer VS is removed in a circumferential marginal region along the edges of the main body and the surface of the main body is exposed there. Moreover, the varistor film VS is removed in the marginal region of the first electrode pair EP1 in order to contact the electrode pair there later. Preferably, the electrodes of the first electrode pair are embodied in each case in a strip-shaped fashion, as is the exposed region.
A second electrode pair EP2 is then applied to the laminated green film of the varistor layer VS such that a respective electrode thereof contacts an electrode of the first electrode pair EP1 in the exposed region. The second electrode pair EP2 is preferably printed, wherein a conductive paste based on silver or copper can be used. After printing, the second electrode pair EP2 can be fired, wherein at the same time the first electrode pair, provided that it is not sintered beforehand, and likewise the terminal pads AF are also concomitantly fired.
In order to produce solderable terminal contacts AK, a passivation layer PS is then applied over the entire surface and structured such that it forms a mask for the production of the terminal contacts AK. A glass-containing layer or some other resist mask, for example a polymer, can be used as passivation layer PS. A glass-containing passivation layer can be printed, for example. A polymer layer, like a photoresist, can be laminated as a film or applied by spin-coating in liquid form and patterned photolitho-graphically.
The external contacts AK can then be applied in an galvanic method. To that end, the second electrode pair EP2, where it is freed of and not covered by the passivation layer PS, is reinforced with a metal of good conductivity, for example with copper. In order to produce a solderable surface, a finishing layer composed of gold, palladium or nickel and/or NiPdAu, NiAu or else CuNiSn can subsequently be applied. Together with this finishing step, if appropriate, the terminal pads AF on the first surface O1 can also be provided with a solderable coating.
In accordance with a second variant, the internal electrode IE is printed onto a first partial film of the varistor layer VS and then a second partial film of the varistor layer is laminated thereabove. This takes place wholly separately from the main body GK, thus giving rise to a prelaminate, which only then is laminated onto the ceramic main body GK.
With the aid of a structuring tool ST, as illustrated in
The varistor layer VS is subsequently sintered, wherein a volume shrinkage commences such as occurs when any ceramic is fired. Since the varistor layer is clamped by the main body, however, this leads at most to little lateral shrinkage, usually none at all, but in return to a reduction of the layer thickness of the varistor layer.
Over the whole area a passivation layer PS is then applied and structured, or is applied in a manner having already been structured or prestructured, for example by printing. The passivation layer PS does not cover the terminal regions provided for connecting the first electrode pair and also parts of the varistor layer VS on which the second electrode pair is produced in a structured fashion later.
In the regions free of the passivation layer PS, the second electrode pair EP2 is then applied, for example by printing. The second electrode pair is subsequently fired.
In order to produce a solderable surface, a finishing layer can be applied to the second electrode pair EP2, for example by electrodeposition of a surface layer OS, for example of a gold, palladium or platinum layer, or of one of the further coatings mentioned above.
The finished component carrier BT can then be equipped with an electrical component, which can be soldered onto the first electrode pair or onto the surface layer OS thereof. Alternatively, the component can also be mounted onto the terminal pads AF on the opposite first top side O1.
A film stack FS is then laminated onto the second surface above the first electrode pair EP1. The method for that can be carried out as already described in the previous exemplary embodiment in accordance with
The film stack FS can be produced remotely from the main body by a procedure in which green films printed with electrode material are laminated one above another such that the internal electrodes IE mutually overlap and electrodes of different polarities can be contacted at marginal regions situated opposite one another. There the individual layers of the internal electrodes also do not overlap another internal electrode of opposite polarity. The laminated film stack FS is subsequently laminated as a whole onto the surface of the main body above the first electrode pair EP1.
In the next step, the second electrode pair EP2 is printed, wherein each of the two electrodes contacts the corresponding underlying electrode of the first electrode pair 1 and also one or more assigned internal electrodes IE. Besides printing, which is preferred, other metallization methods are also conceivable, in principle, e.g. ink jet methods, vapor deposition, sputtering. In the active varistor region, electrodes of different polarities overlap, selected from electrode layers from the second electrode pair EP2, internal electrodes IE and the first electrode pair EP1.
Into these exposed regions, by means of electrodeposition, the second electrode pair EP can then be reinforced or provided with a solderable surface layer OS.
In the embodiment according to
In the embodiment according to
The component BE can be an arbitrary electrical component which is sensitive to overvoltages such as can be triggered e.g. by an ESD pulse, and which is protected against these current or voltage surges with the aid of the varistor function within the varistor layer. One exemplary application is an LED that can be applied as component BE to the component carrier.
The invention has been able to be explained only on the basis of a few exemplary embodiments and is therefore not restricted to the embodiments illustrated. The production methods, in particular, have been illustrated only for an isolated main body intended to be equipped with a component. It is also possible, however, to use a large-area main body GK or a corresponding wafer which can be singulated into a multiplicity of individual component carriers in the latter method step.
Although the electrodes have been illustrated only in pairs, a component carrier is not restricted to those having two electrodes or having two terminal contacts per electrode. For each electrode it is possible to provide a plurality of terminal pads or electrode pairs, which, however, can again be interconnected in parallel among one another.
The varistor layer can be without an internal electrode or be provided with a floating internal electrode or with electrically connected overlapping internal electrodes. The number of internal electrodes enlarges the overlap area of electrodes of opposite polarities and thus determines the capacitance of the varistor.
More overlap area of the electrodes leads to more current-carrying capacity. Doubled ceramic height with internal electrode situated therebetween yields doubled protection level since double the number of microvaristors are then in series. Doubled area yields doubled dissipation capability since double the number of current paths are then in parallel.
Doubled volume of the varistor yields approximately doubled energy absorption capability since double the number of energy absorbers in the form of zinc oxide grains are then available.
The embodiment according to
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2016 100 352 | Jan 2016 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2017/050409 | 1/10/2017 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/121727 | 7/20/2017 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5119062 | Nakamura | Jun 1992 | A |
| 5699035 | Ito | Dec 1997 | A |
| 6608547 | Greier | Aug 2003 | B1 |
| 7768754 | Collins | Aug 2010 | B2 |
| 20050184387 | Collins | Aug 2005 | A1 |
| 20070271782 | Block | Nov 2007 | A1 |
| 20080238604 | Sato | Oct 2008 | A1 |
| 20090045907 | Hoidis | Feb 2009 | A1 |
| 20110261536 | Feichtinger | Oct 2011 | A1 |
| 20130335189 | Abe | Dec 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 102008024480 | Dec 2009 | DE |
| 1111679 | Jun 2001 | EP |
| 2381451 | Oct 2011 | EP |
| 05-072567 | Mar 1993 | JP |
| 2009-252930 | Oct 2009 | JP |
| WO 200004577 | Jan 2000 | WO |
| Entry |
|---|
| International Search Report in International Patent Application No. PCT/EP2017/050409, dated Mar. 21, 2017 (3 pages). |
| Written Opinion in International Patent Application No. PCT/EP2017/050409, dated Mar. 21, 2017 (5 pages). |
| Number | Date | Country | |
|---|---|---|---|
| 20190019604 A1 | Jan 2019 | US |
