The present invention relates to computer systems; more particularly, the present invention relates to compressing data within a computer system.
Currently, various mechanisms are employed to compress data in computer systems. Such methods include adaptive dictionary based algorithms. Dictionary based algorithms feature scanning a data block to be compressed in order to find frequently used values (or redundancies). The redundancies are replaced in the data block with pointers to various locations within a dictionary table, where the value is stored. The dictionary and the compressed data block are subsequently transmitted. Once received the data block is decompressed by reinserting the redundant values in place of the pointers.
Existing dictionary-based compression methods (such as X-Match, Wilson-Kaplan and the LZ variants) serially decompress each symbol in a compressed block. Thus, random access into the compressed block is precluded. The additional latency due to serial access makes existing dictionary-based compression methods undesirable for latency-sensitive applications that require fast random access.
The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
A compression-decompression mechanism is described. In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
A chipset 107 is also coupled to bus 105. Chipset 107 includes a memory control hub (MCH) 110. MCH 110 may include a memory controller 112 that is coupled to a main system memory 115. Main system memory 115 stores data and sequences of instructions and code represented by data signals that may be executed by CPU 102 or any other device included in system 100.
In one embodiment, main system memory 115 includes dynamic random access memory (DRAM); however, main system memory 115 may be implemented using other memory types. Additional devices may also be coupled to bus 105, such as multiple CPUs and/or multiple system memories.
In one embodiment, MCH 110 is coupled to an input/output control hub (ICH) 140 via a hub interface. ICH 140 provides an interface to input/output (I/O) devices within computer system 100. For instance, ICH 140 may be coupled to a Peripheral Component Interconnect bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg.
According to one embodiment, a cache memory 103 resides within processor 102 and stores data signals that are also stored in memory 115. Cache 103 speeds up memory accesses by processor 102 by taking advantage of its locality of access. In another embodiment, cache 103 resides external to processor 103.
According to a further embodiment, cache 103 includes compressed cache lines to enable the storage of additional data within the same amount of area. In such an embodiment, the cache lines are compressed via a Parallel Dictionary Decompression (PDD) compression mechanism.
In one embodiment, PDD is effective on program heap data and on small block sizes (e.g., 64-128 bytes) by taking advantage of redundancies typically found in program data (e.g., redundancies in the upper bits of pointers and small integer values). PDD compresses a fixed-size block of data serially (e.g., one 4-byte dword or 8-byte chunk per clock).
The result of compressing a block is a fixed-size compressed block with a size that depends on the compression ratio. In one embodiment, a compressed block includes a fixed number of compressed symbols (each of which is a compressed representation of a 32-bit word in the uncompressed block) and a fixed number of dictionary elements.
Tags within a compressed symbol indicate a type of decompression being used. Table 1 shows an example encoding for the tags in the compressed block illustrated in
If Ti=00, a 0-extension of the unmatched bits Ci occurs. For example, if T15 is 0 and C15 is 1, the first word is 1, which is preceded by all zeroes. If Ti=01, a 1-extension of the unmatched bits Ci occurs. For example, if T15 and C15 is 1, the first word has a negative value (depending on the width of C), which is preceded by all ones. If Ti=10, the unmatched bits Ci are appended to the bits of dictionary element D0. Similarly, if Ti=11, the unmatched bits Ci are appended to the dictionary element D1.
In contrast to existing compression mechanisms, which have a variable compression ratio to compress by as much as possible, PDD has a fixed compression ratio. fixed compression ratio suits applications that manage memory fixed in chunks and require fast decompression latency. For instance, cache memory is organized and managed in 64 or 128-byte sectors so that variable decompression ratio leads to fragmentation (e.g., unused space in the compressed block). Although described with reference to a cache compression application, one of ordinary skill in the art will appreciate that the PDD compression mechanism may be implemented in other applications (e.g., such as memory and bus compression, and network packet compression).
The compression ratio of PDD depends on several design parameters including the size of the block being compressed, the number of dictionary elements, and the size of each dictionary element. The design parameters can be tuned to meet the compression ratio requirements of the target application for which compression is being used, and to maximize the number of blocks compressed in the target workloads.
According to one embodiment, PDD compresses one 32-bit symbol per clock cycle. At iteration i, the ith symbol Si (held in register RS) is split into its upper 21 bits (signal Ui) and its bottom 11 bits (the unmatched bits Ci). Ui is compressed into a tag Ti, which is accumulated along with Ci in a buffer. Registers RD0 and RD1 hold the two dictionary elements and registers RV0 and RV1 are Booleans that indicate whether RD0 and RD1 hold valid dictionary elements, respectively.
At iteration i, signal Dji is the value of dictionary element RDj and is valid only if signal Vji is true. The initial value of RVj is false, and the initial value of RDj is zero. At each iteration i, logic 420 takes as input the dictionary values Dji, dictionary valid bits Vji, and upper bits of the symbol Ui, and produces the tag Ti for the current iteration as well as the dictionary values Dji+1 and valid bits Vji+1 for the next iteration (i.e., iteration i+1).
In one embodiment, the RV and RD registers load new values upon each iteration. The not compressible signal (NC) is set to true, if Ui is not compressible (e.g., Ui cannot be compressed via sign extension, it does not match any values in the dictionary elements, and the dictionary elements are all valid).
After 16 iterations, the buffer holds the 16 compressed symbols (208 bits of data), and the dictionary registers, RD0 and RD1, hold the dictionary elements. The dictionary registers and buffer 430 are combined to form the compressed block, regardless of the values in RV0 and RV1 (sometimes dictionary elements are unused in a compressed block, indicated by a false value in RV0 or RV1).
The and-gate and nor-gate in logic 510 determine whether the bits are all ones, or all zeroes, respectively. If all ones, the data is compressed via one extension. If all zeroes, the data is compressed via zero extension. If the bits are not all ones, all zeroes, or do not match any of the dictionary elements, a no match signal is transmitted to no match logic 520. No match logic 520 is used to store the unmatched bits in the next dictionary entry. One of ordinary skill in the art will appreciate that other types of logic circuitry may be used to implement the components of logic 420.
Tag encoder 550 uses the match, sign-extension, and valid signals to generate the tag value according to the encoding of Table 1. Table 2 shows a truth table for tag encoder 550.
In one embodiment, the critical path in
In one embodiment, the number of dictionary elements may be varied.
Therefore, using PDD enables picking a fixed number of leading bits to match and automatically derive the number of dictionary elements available. In another embodiment, the number of desired dictionary elements can be fixed in order to solve for the leading bits allowed in partial matches and sign extension.
According to other embodiments, the format of a compressed block can also be varied. For example, the dictionary elements can be placed in the middle of the compressed block or at either ends of the compressed block. If the compressed block is transmitted serially over a bus, then placing the dictionary elements at the beginning of the compressed block allows decompression to be overlapped with arrival of the compressed data.
If the compressed block is available in parallel, then placing the dictionary elements in the middle of the block minimizes delays in distributing the elements to the decompression units. In a further embodiment, the dictionary elements may be replicated throughout the compressed block. Replicating the dictionary elements to provide efficient access to all segments of the block.
In another embodiment, different methods of combining unmatched bits with dictionary elements may be implemented, as well as different methods of sign-extending unmatched bits to handle data types such as packed 8 or 16-bit integers, unicode characters (Utf16), aligned pointers, and floating point. For example, the compression logic can divide a 32-bit dword into 216-bit halves and compress each half's leading sign bits. Compression can also be combined with power optimizations by inverting the dictionary elements and unmatched bits to maximize zeroes. The inversion can be encoded in the tags.
Referring back to
The latency to produce a decompressed symbol Si equals the delay to distribute the dictionary elements D0 and D1 to Si's decompression unit, plus the latency of the decompression unit. In one embodiment, unmatched bits are each 11 bits; therefore, dictionary elements are each 21 bits, and the compressed block is 250 bits. The decompressed block is 512 bits for a compression ratio of slightly better than 2:1. Thus, such an embodiment is suitable for compressing 64 byte data, such as cache lines, down to 32 bytes. However, one of ordinary skill in the art will appreciate that other size data blocks, dictionary elements and compression ratios may be implemented without departing from the true scope of the invention.
The PDD mechanism enables dictionary based data blocks to be decompressed in parallel, thus various data within the block may be randomly decompressed and access without having to wait for the entire block to be decompressed. Accordingly, latency-sensitive applications, such as cache line compression, may implement PDD without incurring performance losses.
Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.