Claims
- 1. In a control device for an elevator system comprising a central processing unit, a first read-only memory for storing a first set of program instructions for computing output control signals for operating controlling means of said elevator system in response to input instructing signals to said central processing unit, an output circuit for communicating said output control signals to said controlling means, a first random access memory for storing said output control signals produced as a result of execution of said first set of program instructions immediately prior to said output control signals being communicated to said controlling means by said output circuit, and address and data buses for connecting said first read-only memory, said output circuit, and said first random access memory with said central processing means, the improvement comprising: a second read-only memory and a second random access memory, said second read-only memory and said second random access memory being connected to said central processing means by said address and data buses, said second read-only memory containing a second set of program instructions for selectively modifying said output control signals produced as a result of said first set of program instructions.
- 2. The control device of claim 1, including means for first storing results of said central processing means executing said first set of programming instructions in said second random access memory, including means for selectively modifying said stored results as a result of said central processing means executing said second set of programming instructions, and including means for transferring said modified results to said first random access memory as said output control signals for communication by said output circuit to said controlling means.
- 3. The control device of claim 2, wherein the storage capacity of said second read-only memory is significantly less than the storage capacity of said first read-only memory.
- 4. The control device of claim 3, further comprising means for selectively inhibiting execution by said central processing means of said second set of program instructions so as to prevent the selective modifying of said stored results.
Parent Case Info
This ia a division of application Ser. No. 224,236, filed Jan. 12, 1981, and now U.S. Pat. No. 4,410,959.
US Referenced Citations (5)
Foreign Referenced Citations (6)
Number |
Date |
Country |
1408666 |
Oct 1975 |
GBX |
1459177 |
Dec 1976 |
GBX |
1486199 |
Sep 1977 |
GBX |
1497158 |
Jan 1978 |
GBX |
1550238 |
Aug 1979 |
GBX |
1571736 |
Jul 1980 |
GBX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
224236 |
Jan 1981 |
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