Claims
- 1. A computer memory system connectable to a processor and having one or more programmable operational characteristics, said characteristics being defined through configuration by said computer based on the type of said processor, wherein said system is connectable to said processor by a bus, said system comprising:
- a main memory connected to said bus; and
- a cache connected to said bus;
- wherein a programmable operational characteristic of said system determines a type of data stored by said cache.
- 2. The system of claim 1 wherein a programmable operational characteristic of said system determines whether said cache stores only code data or whether said cache stores both code data and non-code data.
- 3. The system of claim 1 wherein a bus master is also connectable to said bus so that both said processor and bus master have access to said memory system, wherein said cache performs buffering of data writes to said main memory, and wherein a programmable operational characteristic of said system determines whether said cache performs buffering of data solely from said bus master or whether said cache performs buffering of data both from said bus master and said processor.
- 4. The system of claim 1 further comprising:
- one or more additional caches connected to said bus;
- wherein a programmable operational characteristic of said system determines a source of data received by at least one of said additional caches.
- 5. The system of claim 4 wherein a bus master is also connectable to said bus so that both said processor and bus master have access to said memory system, wherein a first programmable operational characteristic of said system determines whether said cache stores only code data or whether said first cache stores both non-code data and code data, wherein one of the additional caches performs buffering of data writes to said main memory, and wherein a second programmable operational characteristic of said system determines whether said one of the additional caches performs buffering of data solely from said bus master or whether said one of the additional caches performs buffering of data both from said bus master and said processor.
- 6. A computer memory system connectable to a processor and having one or more programmable operational characteristics, said characteristics being defined through configuration by said computer based on the type of said processor comprising:
- a main memory, connected to said processor by a bus, including a plurality of pages of a first type and a plurality of pages of a second type; and
- a register connected to said memory for holding a page address of a most recently accessed one of said first type pages;
- wherein said page address is used to reopen the most recently accessed one of said first type pages after one of said second type pages has been accessed; and
- wherein a programmable operational characteristic of said system determines a type of data stored in said main memory.
- 7. The system of claim 6 wherein a programmable operational characteristic of said system determines a type of data stored in said first and second type pages; and wherein the type of data includes code and non-code data.
- 8. A computer memory system, connectable to a processor and bus master by a bus and having programmable operational characteristics based on characteristics of said processor, comprising:
- a plurality of caches connected to said bus;
- a main memory connected to said bus and including a plurality of pages of a first and second type; and
- a register connected to said memory for holding the page address of the most recently accessed of said first type pages;
- wherein a first programmable characteristic of said system determines whether a first of said caches stores only code data or whether said first of said caches stores both non-code data and code data;
- wherein a second of said caches performs buffering of data writes to said main memory, and a second programmable characteristic of said system determines whether said second of said caches performs buffering of data solely from said bus master and whether said second of said caches performs buffering of data both from said bus master and said processor;
- wherein said page address is used to reopen a most recently accessed of said first type pages after one of said second type pages has been accessed; and
- wherein a third programmable operational characteristic of said system determines a type of data stored by said main memory.
- 9. The system of claim 8 wherein a programmable operational characteristic of said system determines a type of data stored said first and second type pages; and wherein the type of data includes code and non-code data.
Parent Case Info
This is a continuation of application Ser. No. 07/563,214 filed on Aug. 6, 1990, now abandoned.
US Referenced Citations (13)
Non-Patent Literature Citations (1)
Entry |
Computer Design, Jul. 1, 1990, pp. 78-90; Wilson: "Will the search for the ideal memory architecture ever end?". |
Continuations (1)
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Number |
Date |
Country |
Parent |
563214 |
Aug 1990 |
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