Computer

Abstract

A computer capable of easily obtaining RTL of a TOP circuit after a block circuit is separated out of the TOP circuit. A port information input unit inputs the port information of the TOP circuit described in RTL, and the port information of block circuits composing the TOP circuit, from a user. A separation information input unit inputs separation information specifying a block circuit to be separated out of the TOP circuit, from the user. A separation port information creation unit creates separation port information after the block circuit is separated, by changing the port information of the TOP circuit and the block circuits based on the port information of the block circuit to be separated according to the separation information. An RTL rewriting unit rewrites RTL of the TOP circuit from which the block circuit has been separated, based on the separation port information created by the separation port information creation unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show the outline of a computer.

FIG. 2 shows an example of a circuit described in RTL.

FIG. 3 is a diagram for explaining how a computer separates an IP macro.

FIG. 4 is a diagram for explaining how a computer adds an IP macro.

FIG. 5 is a diagram for explaining how a computer adds and separates IP macros.

FIGS. 6 and 7 are a flowchart describing how a computer separates, adds, and adds and separates IP macros.

FIG. 8 is a functional block diagram of the computer.

FIG. 9 shows a circuit before the computer separates an IP macro.

FIG. 10 shows a circuit after the computer separates the IP macro.

FIG. 11 shows a port information file of TOP1 to be inputted to the computer.

FIG. 12 shows a port information file of FUNC1 to be inputted to the computer.

FIG. 13 shows a port information file of FUNC2 to be inputted to the computer.

FIG. 14 shows a port information file of IP1 to be inputted to the computer.

FIG. 15 shows a setting file to be inputted to the computer.

FIG. 16 shows a port information file of TOP1 after the separation.

FIG. 17 shows a port information file of FUNC1 after the separation.

FIG. 18 shows a port information file of FUNC2 after the separation.

FIGS. 19 and 20 show RTL of TOP1 to be inputted to the computer.

FIG. 21 shows RTL of IP1 to be inputted to the computer.

FIG. 22 shows RTL of TOP1 after the separation of IP1.

FIG. 23 is a flowchart describing how to create port information files when an IP macro is separated.

FIG. 24 shows a circuit before the computer adds an IP macro.

FIG. 25 shows a circuit after the computer adds the IP macro.

FIG. 26 shows a port information file of TOP2 to be inputted to the computer.

FIG. 27 shows a port information file of IP2 to be inputted to the computer.

FIG. 28 shows a setting file to be inputted to the computer.

FIG. 29 shows a port information file of TOP3 after the addition.

FIG. 30 shows a port information file of FUNC1 after the addition.

FIG. 31 shows a port information file of FUNC2 after the addition.

FIG. 32 shows RTL of IP2 to be inputted to the computer.

FIGS. 33 and 34 show RTL of TOP3 after IP2 is added.

FIG. 35 is a flowchart describing how to create port information files when an IP macro is added.

FIG. 36 shows conversion of a port format.

FIG. 37 is a diagram of a circuit to be realized by an ASIC.

FIG. 38 is a diagram of a circuit from which an IP macro has been separated.

Claims

1. A computer for designing a circuit, comprising: port information input means for inputting port information of a TOP circuit described in register transfer level (RTL) and block circuits composing the TOP circuit;separation information input means for inputting separation information specifying a separation block circuit to be separated out of the TOP circuit;separation port information creation means for creating separation port information after the separation block circuit is separated, by changing the port information of the TOP circuit and the block circuits based on the port information of the separation block circuit to be separated according to the separation information; andRTL rewriting means for rewriting the RTL of the TOP circuit from which the separation block circuit has been separated, based on the separation port information.

2. The computer according to claim 1, wherein the port information includes names of ports, names of connection circuits to which the ports are connected, and names of connection ports to which the ports are connected.

3. The computer according to claim 2, wherein the separation port information creation means obtains, from the port information of the separation block circuit, a connection circuit name that identifies any one of the block circuits and a connection port name associated with the obtained connection circuit name, searches the port names of the port information of the block circuit identified by the obtained connection circuit name, to find a port name that is identical to the obtained connection port name, and changes a connection circuit name associated with the found port name, to the TOP circuit.

4. The computer according to claim 3, wherein the separation port information creation means further changes to the obtained connection port name a connection port name associated with the found port name in the port information of the block circuit identified by the obtained connection circuit name.

5. The computer according to claim 1, further comprising: addition information input means for inputting addition information specifying an addition block circuit to be added to the TOP circuit;addition port information creation means for creating addition port information after the addition block circuit is added, by changing the port information of the TOP circuit and the block circuits based on the port information of the addition block circuit to be added according to the addition information; andRTL creation means for creating the RTL of the TOP circuit with the addition block circuit added thereto, based on the addition port information.

6. The computer according to claim 5, wherein the port information has information including names of ports, names of connection circuits to which the ports are connected, and names of connection port to which the ports are connected.

7. The computer according to claim 6, wherein the addition port information creation means obtains, from the port information of the addition block circuit, a connection circuit name that identifies any one of the block circuits, and a connection port name and a port name associated with the obtained connection circuit name, searches the port names of the port information of the block circuit identified by the obtained connection circuit name, to find a port name that is identical to the obtained connection port name, and changes a connection circuit name associated with the found port name, to the addition block circuit.

8. The computer according to claim 7, wherein the addition port information creation means further changes to the obtained port name a connection port name associated with the found port name in the port information of the block circuit identified by the obtained connection circuit name.

9. The computer according to claim 6, wherein, in a case where a connection circuit name of the port information of the addition block circuit specifies a prescribed state, the RTL rewriting means rewrites the RTL so as to get a port identified by a port name associated with the connection circuit name into the prescribed state.

10. The computer according to claim 1, further comprising a circuit scale dividing means for dividing the TOP circuit if the TOP circuit exceeds a circuit scale allowable in a device.

11. The computer according to claim 1, further comprising pin quantity dividing means for dividing the TOP circuit if the TOP circuit exceeds the number of pins allowable in a device.