BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a CNC system of prior art.
FIG. 2 is a block diagram showing access to a shared memory by a human interface computer in the CNC system of FIG. 1.
FIG. 3 is a block diagram showing another CNC system of prior art using a Dual Port RAM.
FIG. 4 is a block diagram showing a CNC system of the present invention.
FIG. 5 is a block diagram showing read access through the PCI bus and motor control communication through the local bus in the CNC system of FIG. 4.
FIG. 6 is a block diagram showing one example of a dual bus memory controller in FIG. 4.
FIG. 7 is a block diagram showing write access through PCI and local buses in the dual bus memory controller of FIG. 6.
FIG. 8 is a block diagram showing read access through PCI and local buses in the dual bus memory controller of FIG. 6.
FIG. 9 is timing diagrams showing read and write transaction from PCI and local buses in the dual bus memory controller of FIG. 6.
FIG. 10 is a block diagram showing one example of FIFO buffer in FIG. 6.
FIG. 11 is a block diagram showing one example of a memory controller in FIG. 6.
FIG. 12 is a block diagram showing concurrent transactions through PCI and local buses in the dual bus memory controller of FIG. 6.
FIG. 13 is timing diagrams showing concurrent read and write transaction from PCI and local buses in the dual bus memory controller of FIG. 6.
DETAILED DESCRIPTION OF THE INVENTION
An exemplary embodiment of a CNC system of the present invention will now be described with reference to the drawings. Similar elements are labeled with similar reference numerals as used in FIGS. 1-3, their detailed explanation will be omitted.
In this invention, a shared memory is not controlled by the embedded processor 30 anymore. It is controlled by a hardware module 2 that is implemented in hardware description language using FPGA (Field Programmable Gate Array) technology. As shown in FIG. 4, this hardware module 2 is named dual bus memory controller and is coupled between the PCI bus 4 and the local bus 34. Both of the human interface computer 1 and the embedded processor 30 are not granted access to buses 4 and 34. The dual bus memory controller 2 is configured for concurrent communication with the PCI bus 4 and the local bus 34 and is adapted to couple to shared memory modules 10 and 11 both of which are shared by the human interface computer 1 and the embedded processor 30. As a result of this design, the local bus 34 is free for the embedded processor 30 to communicate with motor drivers 6 without wait time while the human interface computer 1 carries out a write/read access to the shared memory 10 or 11 through the PCI bus 4, as shown in FIG. 5. As a result, a higher performance of controlling the motor's motion controlling is provided.
As shown in FIG. 6, the dual bus memory controller 2 includes an expansion bus interface 21, an external bus interface 29 and memory controllers 24 and 26. The first memory controller 24 is coupled to the first shared memory 10 and the second memory controller 26 is coupled to the second shared memory 11. The expansion bus interface 21 is operable to interface the PCI bus 4 to the shared memories 10 and 11 while an external bus interface 29 is operable to interface with the local bus 34 to the shared memories 10 and 11. The PCI bus interface 21 allows the human interface computer 1 to issue read/write access to the first memory controller 24. But, it allows the human interface computer 1 to issue only a read access to the second memory controller 26. On the other hand, the external bus interface 29 allows the embedded processor 30 to read data from or write data to the second memory controller, but it allows the embedded processor 30 only to read data from the first memory controller 24. Thus, the dual bus memory controller 2 prohibits a write access to the second memory 11 from the human interface computer 1 and a write access to the second memory 11 from the human interface computer 1 and a write access to the first shared memory 10 from the embedded processor 30. Alternatively, the human interface computer 1 may limit a write access to the second shared memory 11 and the embedded processor 30 may limit a write access to the first shared memory 10. Though most of FPGA products in a computerized numerical control system provides use of a Dual Port RAM, each of the shared memories 10 and 11 is a low cost SDR SDRAM or DDR SDRAM, and they are meant for massive data transfer. Each of the shared memories 10 and 11 may be SRAM. Beside the shared memories 10 and 11, a DPBRAM (Dual Port Block Random Access Memory) module 25 in FPGA is used to provide a small shared data area for fast read/write access from both the human interface computer 1 and embedded processor 30. This memory area is meant to store control words at faster transaction and lower latency rates than the shared memories 10 and 11. In addition, four FIFO buffer (first-in-first-out buffer) modules 22, 23, 27 and 28 are used to buffer the data from the buses 4 and 34 to the memory controllers 24 and 26. They are exactly same module with write/read control signals for read-only control. The FIFO buffer 22 is coupled between the PCI bus interface 21 and the first memory controller 24 and the FIFO buffer 23 is coupled between the PCI bus interface 21 and the second memory controller 26. The FIFO buffer 27 is coupled between the external bus interface 29 and the first memory controller 24 and the FIFO buffer 28 is coupled between the external bus interface 29 and the second memory controller 26.
As shown in FIG. 7, while the human interface computer 1 writes instruction data such as an NC program to the first shared memory 10 through the first memory controller 24, the embedded processor 30 also can access to the second shared memory 11 through the second memory controller 26 to updated feedback data. Data is written in to the shared memories 10 and 11 through the PCI bus 4 and the local bus 34 concurrently. As shown in FIG. 8, the embedded processor 30 reads the NC program from the first shared memory 10 through the first memory controller 24 while feedback data is read from the second shared memory 11 through the second memory controller 26 by the human interface computer 1 and displayed on the graphical user interface. FIG. 9 illustrates the PCI bus transaction and the local bus transaction occurring concurrently, and the first and second memory controllers 24 and 26 issue read and write transfer with the first and second shared memories 10 and 11. Because of the dual memory module architecture, concurrent read or write on different shared memories is possible.
In the case of accessing the same shared memory by two bus interfaces 21 and 29 at the same time, FIFO buffers will work as temporary storage for data and the memory controllers 24 and 26 arbitrate priority of accesses from the buses 4 and 34. Three different clocks are used in the embodiment, a memory clock, a local bus clock, and an expansion bus clock which is a PCI bus clock. The FIFO buffers 22, 23, 27 and 28 are the main modules to synchronize and buffer data. As shown in FIG. 10, each FIFO buffer 22, 23, 27 and 28 includes three asynchronous FIFOs 221, 222 and 223 and a FIFO controller 224. The asynchronous FIFOs 221, 222 and 223 allow data synchronization from the buses 4 and 34 to the memory controllers 24 and 26. The write FIFO 221 is a first-in-first-out buffer that stores and synchronizes data from the bus interface 21 or 29 to the memory controller 24 or 26. The address FIFO 222 is exactly same as the write FIFO 221. The only difference is that the address FIFO 222 stores and synchronizes address location of the data in write transaction. When data is written into the shared memory 10 or 11, the data and its memory location (address) are stored in the write FIFO 221 and the address FIFO 222, respectively. The FIFO controller 224 is a state machine that controls the all FIFOs 221, 222 and 223 in a FIFO buffer 22. It also generates the FIFO status signals such as write FIFO not-empty signal. These status signals inform the memory controller 24 or 26 to start a memory write transaction and data is written into the shared memory 10 or 11. During a read transaction, request address is loaded into the address FIFO 222. The memory controller 24 or 26 serves a request and read data into the read FIFO 223. Then, requested read data is synchronized and sent to the bus interface 21 or 29. If the memory controller 24 or 26 is operating other transactions for the other bus, data and its address locations are stored in the write FIFO 221 and address FIFO 222 until the memory controller 24 or 26 serves the transaction in the FIFO buffer. The priority of transactions is determined by an arbiter module 244 in each memory controller 24 and 26 in FIG. 11.
The first and second memory controllers 24 and 26 have the same architecture shown in FIG. 11. Each memory controller 24 and 26 is a dual port memory controller that allows two address data buses to be connected to it. It contains a memory interface module 241 which interfaces data and address bus with the shared memory 10 or 11. In addition, different type of memory module can be used in one computerized numerical control system by implementing different type of the memory interface 241. The arbiter 244 determines the priority of bus requests. It sends a select signal to a multiplexer module 242 to switch a different bus request to the memory interface 241. During read transactions, the memory interface 241 serves the read request from address bus and send read data to a demultiplexer module 243. Then, the arbiter module 244 selects the data path to the bus interface 2 or 29. When the PCI bus 4 requests a write transaction and the local bus 34 requests a read transaction at the same time, the FIFO buffer 22 stores the write data from the PCI bus 4. And, the first memory controller 24 reads data from the first shared memory 10 to the FIFO buffer 27. The PCI bus interface 21 will not stop the write transaction from the PCI bus 4 unless the FIFO buffer 22 is full. After the first memory controller 24 fills the read FIFO 223 in the FIFO buffer 27, it will store the write data into the first shared memory 10. As a result, both local bus transaction and PCI bus transaction can be active at the same time with no influence to the others, a shown in FIG. 12. If the FIFO buffer 22 is full, the PCI bus 4 will need to issue a stop signal. To minimize the number of stop or retry in a transaction, the size of the write FIFO 221 in FIG. 10 should be as large as possible. On the other hand, the size of the read FIFO 223 in FIG. 10 should not be larger than the maximum size of a memory burst read. Also, memory transfer speed should be two times of the bus transfer speed.
FIG. 13 shows an example of concurrent transactions from the PCI bus 4 and local bus 34. In the example, memory clocks are running at two times faster than bus clocks and the local bus 34 has the same speed of the PCI bus 4. Also, each shared memory 10 and 11 has a 4 words burst read access. Because the local bus 34 is designed to have higher priority, the memory controller 24 firstly reads data from the shared memory 10 and stores the data into the FIFO buffer 27. The memory controller 24 secondly reads data that is stored in the FIFO buffer 22, and it sends the data to the shared memory 10. At this point, the first read transaction of the local bus 34 and write transaction of the PCI bus 4 are served. The memory controller 24 accepts the read request from the PCI bus 4 and reads data from the shared memory 10 immediately because the local bus 34 is still reading data from the FIFO buffer 27. The memory controller 24 sends request data to the FIFO buffer 22 while the external bus interface 29 requests another read transaction from the shared memory 10. The second request from the external bus interface 29 starts after the memory controller 24 sends read data to the FIFO buffer 22. At last, the memory controller 24 serves write transaction from the PCI bus interface 21. If a read transaction from the local bus 34 happens during the last write transaction, the memory controller 24 will stop the write transaction. The write transaction is restarted after the read transaction is completed. In the case of read/write control words for motor control, the dual port block RAM 25 located in FPGA is taking part in the transaction.
The present invention is not intended to be limited to the disclosed form. It is clear that many improvements and variations are possible with reference to the above description. The illustrated embodiment was selected to explain the essence and practical application of the invention. The scope of the invention is defined by the attached claims.
Patent Application
20080065837
