Modern computing increasingly takes place in data center environments. Particularly with the rise of large machine learning (ML) models, the need for increased compute power has risen dramatically. The cost of deploying and operating compute units used to handle computing tasks such as model training and inference is significant. Further, the compute time required to train large ML models can be lengthy and costly. As a result, technical challenges exist to improve data center hardware, to increase performance and control costs, for the increasing compute demands of the modern ML era.
To address the above issues, a computing device assembly is provided. According to a first aspect, a computing device assembly is provided, including a rack, and a plurality of compute units that are horizontally oriented and mounted within the rack in one of two vertical stacks. The computing device assembly further includes a plurality of switches that are vertically oriented and mounted along a front side of the rack laterally between the two vertical stacks of compute units. The computing device assembly further includes a plurality of horizontal cable backplanes mounted in a vertical stack along a rear side of the rack. The computing device assembly further includes a plurality of vertical cable shuffles mounted between the two vertical stacks of compute units and between the vertically oriented switches and the vertical stack of horizontal cable backplanes.
According to a second aspect, the computing device assembly includes a rack defining a rectangular volume, a plurality of compute units, each computing unit being horizontally oriented and mounted within the rack in one of two vertical stacks positioned on opposite lateral sides of the rack. The computing device assembly further includes a plurality of switches, each switch being vertically oriented and mounted within the rack along a front side of the rack laterally between the two vertical stacks of compute units, in one of a plurality of groups positioned at respective vertical levels. The computing device assembly further includes a plurality of horizontal cable backplanes mounted in a vertical stack along a rear side of the rack, each horizontal cable backplane containing cables that electrically interconnect a compute unit from the first stack, a compute unit from the second stack and a switch at a corresponding vertical level. The computing device assembly further includes a plurality of vertical cable shuffles mounted within the rack so as to be between the two vertical stacks of compute units in a lateral dimension, and between the vertically oriented groups of switches and the vertical stack of horizontal cable backplanes in a depth (front-rear) dimension, each vertical cable shuffle including cables that electrically interconnect each of a plurality of connections on a corresponding switch from each of the groups of switches to corresponding connections on each of the horizontal cable backplanes.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure.
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The computing device assembly 100 further includes a plurality of switches 16, each switch 16 being vertically oriented and mounted within the rack 10 along a front side 24 of the rack 10 laterally between the two vertical stacks 12A, 12B of compute units 12, in one of a plurality of groups positioned at respective vertical levels. In the depicted embodiment, four groups 16A-16D of switches 16 are illustrated, each at a different level in a vertical dimension 29 of the rack 10. The data connections for the switches 16 are formed on the rear side of the switches 16. The switches 16 are generally the same size, each being elongated in the depth and vertical dimensions 28, 29 of the rack 10, as mounted.
The computing device assembly 100 further includes a plurality of horizontal cable backplanes 14 mounted in a vertical stack along the rear side 22 of the rack 10, each horizontal cable backplane 14 containing cables that electrically interconnect the data connections on the compute unit 12 from the first stack 12A, the compute unit 12 from the second stack 12B and the switch 16 at a corresponding vertical level. The horizontal cable backplanes 14 extend over substantially an entire lateral dimension of the rack 10, and the data connections for the horizontal cable backplanes 14 are positioned to face the front side 24 of the rack 10, thus facing the data connections on the rear side of the compute units 12.
The computing device assembly 100 further includes a plurality of vertical cable shuffles 20 mounted within the rack 10 so as to be between the two vertical stacks 12A, 12B of compute units 12 in the lateral dimension 26, and between the vertically oriented groups 16A-16D of switches 16 and the vertical stack of horizontal cable backplanes 14 in the depth dimension 28. Each of the vertical cable shuffles 20 includes cables that electrically interconnect data connections of each of a plurality of data connections on a corresponding switch from each of the groups 16A-16D of switches 16 to corresponding data connections on each of the horizontal cable backplanes 14. The vertical cable shuffles 20 typically include housings of folded sheet metal with internal cabling 48 (see
It is believed that the above described computing device assembly 100 provides a technical benefit when used with high data transfer rate machine learning applications, such as large ML model training and inference, at speeds on the order of 100 gigabit per second and higher using a passive channel within a rack configured in the manner of rack 10 described above, thereby improving the compute time required to train such models. Such speeds on passive channels can be reached due to the efficiency of cable routing afforded by the arrangement of components within rack 10.
The following paragraphs provide additional description of the subject matter of the present disclosure. One aspect provides a computing device assembly including a rack, a plurality of compute units, a plurality of switches, a plurality of horizontal cable backplanes, and a plurality of vertical cable shuffles. According to this aspect, the plurality of compute units may be horizontally oriented and mounted within the rack in one of two vertical stacks. The plurality of switches may be vertically oriented and mounted along a front side of the rack laterally between the two vertical stacks of compute units. The plurality of horizontal cable backplanes may be mounted in a vertical stack along a rear side of the rack. The plurality of vertical cable shuffles may be mounted between the two vertical stacks of compute units and between the vertically oriented switches and the vertical stack of horizontal cable backplanes.
According to this aspect, data connections for the horizontal cable backplanes may be positioned to face the front side of the rack, and to face data connections on a rear side of the compute units.
According to this aspect, the horizontal cable backplanes may extend over substantially an entire lateral dimension of the rack.
According to this aspect, the vertical cable shuffles may be elongated in depth and height dimensions of the rack.
According to this aspect, the vertical cable shuffles each may include a housing of folded sheet metal with internal cabling.
According to this aspect, data connections on the vertical cable shuffles may face both the rear side of the rack and the front side of the rack.
According to this aspect, a lateral dimension of each of the compute units may be approximately ¼ to ⅓ of a lateral dimension of the rack, and a depth dimension of each of the compute units may be approximately 60-90% of the rack.
According to this aspect, the depth dimension of each of the compute units may be approximately 70-80% of the rack.
According to this aspect, each of the switches may be elongated in vertical and depth dimensions of the rack.
According to this aspect, the computing device assembly may further include power conversion units mounted in mounting bays adjacent lateral sides of the rack.
According to this aspect, the plurality of compute units may include 64 compute units or more.
According to another aspect of the present disclosure, a computing device assembly is provided. According to this aspect, the computing device assembly may include a rack defining a rectangular volume. The computing device assembly may further include a plurality of compute units, in which each computing unit may be horizontally oriented and mounted within the rack in one of two vertical stacks positioned on opposite lateral sides of the rack. The computing device assembly may further include a plurality of switches, in which each switch may be vertically oriented and mounted within the rack along a front side of the rack laterally between the two vertical stacks of compute units, in one of a plurality of groups positioned at respective vertical levels. The computing device assembly may further include a plurality of horizontal cable backplanes mounted in a vertical stack along a rear side of the rack, in which each horizontal cable backplane contains cables that electrically interconnect a compute unit from a first stack of the two vertical stacks, a compute unit from a second stack of the two vertical stacks, and a switch at a corresponding vertical level. The computing device assembly may further include a plurality of vertical cable shuffles mounted within the rack so as to be between the two vertical stacks of compute units in a lateral dimension, and between the vertically oriented groups of switches and the vertical stack of horizontal cable backplanes in a depth dimension. Each vertical cable shuffle may include cables that electrically interconnect each of a plurality of connections on a corresponding switch from each of the groups of switches to corresponding connections on each of the horizontal cable backplanes.
According to this aspect, the vertical cable shuffles may be elongated in depth and height dimensions of the rack.
According to this aspect, data connections on the vertical cable shuffles may face both the rear side of the rack and the front side of the rack.
According to this aspect, a lateral dimension of each of the compute units may be approximately ¼ to ⅓ of a lateral dimension of the rack, and a depth dimension of each of the compute units may be approximately 60-90% of the rack.
According to this aspect, the depth dimension of each of the compute units may be approximately 70-80% of the rack.
According to this aspect, each of the switches may be elongated in vertical and depth dimensions of the rack.
According to this aspect, the computing device assembly may further include power conversion units mounted in mounting bays adjacent lateral sides of the rack.
According to this aspect, the vertical cable shuffles each may include a housing of folded sheet metal with internal cabling.
According to this aspect, the plurality of compute units may include 64 compute units or more.
“And/or” as used herein is defined as the inclusive or ∨, as specified by the following truth table:
It will be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated and/or described may be performed in the sequence illustrated and/or described, in other sequences, in parallel, or omitted. Likewise, the order of the above-described processes may be changed.
The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.
This application claims priority to U.S. Provisional Patent Application Ser. No. 63/609,786, filed Dec. 13, 2023, the entirety of which is hereby incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63609786 | Dec 2023 | US |