Patent Application
20060245264
The present invention relates to computers and, more particularly, to error-handling in computers. In this specification, related art labeled “prior art” is admitted prior art; related art not labeled “prior art” is not admitted prior art.
Applications for which errors are unacceptable can be run on computers that detect and address errors that inevitably occur. For example, parity bits or error-correction code bits can be added to data being communicated so that errors can be detected and, in some cases, corrected. If the errors cannot be corrected, often the data can be regenerated or retransmitted. However, it is generally impractical to employ error detection and error correction extensively within a processor. Accordingly, data corruptions occuring with in a processor are often undetected, i.e., “silent”.
Such silent data corruption can be addressed by running two or more processors in lock-step. In other words, the same program is run on two processors. The processor outputs can then be compared with differences being used to indicate errors, with various approaches being available for addressing the detected errors.
As defined in the claims, the present invention provides for both lock-step and free-step (normal, non-lockstep) operation in the same computer system. Various embodiments of the invention include systems in which the step mode for each processor is fixed, in which step modes can be configured (e.g., upon boot-up), and systems in which the step mode is dynamically reallocable. In each case, the invention provides for more optimal trade-offs between error detection and performance, as operating processors in free-step mode generally provides greater performance at the risk of greater vulnerability to errors. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.
A computer system AP1 shown in
Core electronic component 11 includes loss-of-lockstep logic 21 and interface logic 31; similarly, core electronic component 12 includes loss-of-lockstep logic 22 and interface logic 32. Interface logics 31 and 32 provide for the convention functions of core electronic components, e.g., interfacing processors with the rest of a system. When a set of processors are in lock-step mode, data from the processors is directed to the respective loss-of-lockstep logic (LOL) 21 or 22. Loss-of-lockstep logics initiate error handling procedures when an error is detected as a loss of lockstep, e.g., when the associated processors provide different outputs for the same inputs. When the associated processors are in free-step mode, data from the processors bypasses the associated loss-of-lockstep logic and the core electronics components acts conventionally. Core electronics components 11 and 12 and in particular loss of lockstep logics 21 and 22 include inputs for controlling the step mode, e.g., as directed by operating system 44, per configuration instructions setup by the user of the system partition running that operating system.
In system AP1, core electronic components 11 and 12 are defined on respective substrates distinct from substrates bearing processors P11, P12, P21, P22. In alternative embodiments, various combinations of processors and core electronic components can be formed on common substrates.
As illustrated, core electronic components 11 and 12 interface with the rest of system AP1 via a bus 41. More generally, the interfacing can be done via a combination of buses or a network fabric. The rest of system AP1 includes, among other components, input-output channels 42 and memory 43. Memory 43 includes random access memory, hard disk storage, and other storage media.
Memory 43 stores an operating system 44, processes 45, a configuration database 46, and data 47. Database 46 contains basic lockstep configuration data including: 1) indicating which CPUs are to be in lock-step mode and which should be in free-step mode; 2) some ‘rules’ which can dynamically change this assignment; and 3) a list of processes that should run in lock-step mode. Processes are run in free-step mode by default unless the configuration database indicates otherwise.
Another embodiment could have this default setting reversed. Some of processes 45 belong to the operating system, while others belong to applications. When a process is called, operating system 44 checks configuration database 46 to determine whether to assign that process to a set of processors in lock-step mode or a processor in free-step mode. Some processes may require assignment to a lock-step mode, while others may require free-step mode. For other processes, database 46 can indicate criteria for assigning a process to one step mode or the other. For example, resource utilization and/or time of day data can be factors in determining whether to assign a process to a lock-step processor or a free-step processor.
When system AP1 is booted, operating system 44 checks database 46 for system configuration data to determine which processors are to be assigned to lock-step mode and which are to be assigned to free-step mode. In system AP1, this assignment is done on a set-by-set basis. While system AP1 is running, operating system 44 monitors resource utilization and, if configuration data permits, writes to database 46 to indicate an assignment of step modes to be assumed the next time system AP1 is booted. This feature is most useful for systems with many sets of processors.
If so configured, operating system 44 can also use resource utilization data to dynamically switch processor step modes. For example, when there is excess demand for data integrity, both processor sets can be set to lock step mode. On the other hand, when greater performance is required and data integrity is less critical, both sets can be assigned to free-step mode.
Some of these capabilities are used in method M1, flow-charted in
Method segments S21-S24 operate concurrently with method segments S11-S24. In method segment S21, operating system 44 monitors resource allocation between processors in lock-step mode versus processors in free-step mode. At method segment S22, a determination is made whether the resource utilization is sufficiently balanced. If one mode is stressed, the processor sets can be reallocated at method segment S23; for example, operating system 44 can signal a core electronics component to place its set of processors in the selected step mode. If supply and demand for the step modes are reasonably balanced, the processor modes can be maintained at method segment S24. Depending on the system configuration, the reallocation can take effect upon restart or can be implemented dynamically. Alternatively, system AP1 can be configured to preclude reallocation of step modes.
Reallocation method segments S21-S24 can interact with assignment method segments S11-S14. In particular, resource allocation data generated in method segment S21 can be used in mode assignment method segment S12 to determine which mode a process should be assigned to, e.g., when the configuration data for that process indicates the mode should favor less utilized resources. Likewise, assignment determinations at method segment S12 can be used as raw data in monitoring resource utilization at method segment S21.
The invention provides for embodiments with as few as two processors. In such a case, both processors can operate in lock-step mode or both can operate in free-step, mode. Systems with three processors have more possibilities. One pair can operate in lock-step mode while the third operates in free-step mode. The pair can be fixed or formed from different combinations of processors. Also, all three can operate in lock-step mode in some circumstances. Greater numbers of processors offer more possibilities. In practice, the association of processors to core electronic components limits the combinations of processors that can be run together in lock step. These and other variations upon and modifications to the described embodiment are provided for by the present invention, the scope of which is defined by the following claims.
