BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a functional block diagram of one or more memory devices and a controller.
FIG. 2 is a timing diagram of a SRR operation.
FIG. 3 is a functional block diagram of a 2-rank, ×16 memory subsystem.
FIG. 4 is a timing diagram of a SRR operation in the memory system of FIG. 3.
FIG. 5 is a timing diagram of a concurrent SRR operation in the memory system of FIG. 3.
FIG. 6 is a functional block diagram of a 2-rank, ×32 memory subsystem.
FIG. 7 is a timing diagram of a concurrent SRR operation in the memory system of FIG. 6, using DDR SDRAM.
DETAILED DESCRIPTION
FIG. 1 depicts one or more SDRAM memory devices 100 and a controller 102. The controller may comprise a processor, digital signal processor, micro controller, state machine, or the like, and includes a control circuit 103 that controls SDRAM accesses. The controller 102 directs operations to the SDRAM devices 100 by control signals Clock (CLK), Clock Enable (CKE), Chip Select (CS), Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE), and Data Qualifiers (DQM) as well known in the art. In particular, the SDRAM devices 100 may be grouped in ranks, ordered by the Chip Select signals. The controller 102 provides a plurality of address lines and bank select lines to the SDRAM devices 100 and a bi-directional data bus connects the controller 102 and each SDRAM device 100. Each SDRAM device 100 includes a DRAM array 104, which may be divided into a plurality of banks 106. The DRAM array 104 stores instructions and data, and is read from, written to, and refreshed by control circuit 108, under the direction of the controller 102.
Each SDRAM device 100 may additionally include a mode register 110 and extended mode register 112. An SDRAM device 100 may additionally include identification information 114, such as vendor ID and version number. The identification information 114 may be stored in a register; alternatively, it may be hardwired into the die.
The SDRAM device 100 additionally includes a temperature sensing circuit 116, including one or more temperature sensors such as a thermister 118 disposed adjacent the DRAM array 104 and operative to sense the temperature of the DRAM array die. The contents of the mode register 110 and extended mode register 112, the SDRAM device identification 114 and the output of the temperature sensor 116 are all examples of data that may be read from a SDRAM device 100, but that are not stored in the DRAM array 104. As used herein, such information is referred to as “status information.”
FIG. 2 depicts a timing a diagram of a SRR operation to read status information, according to one embodiment. Initially, a MRS command is issued on the SDRAM control signals, with the bank select bits set to 2′b10 and an address of 0x0 (a read of other status register locations is specified by a different value on the address bus). Following the minimum MRS time tMRS, a conventional READ command is issued. The SDRAM device outputs status information onto the data bus following the programmed CAS latency tCL, in lieu of data from the DRAM array, but otherwise following the timings and sequencing of a conventional SDRAM read operation. A new command may be issued to the SDRAM device following the data transfer of status information.
According to one or more embodiments, when a read of status information requires less than the full N-bit SDRAM data bus, the status information may be advantageously driven on a subset M of the N bits, with the remaining N-M bits being tri-stated during a SRR operation. The information regarding which bits of the data bus to utilize for SRR operations—referred to herein as SRR configuration information—is written by the controller 102 to a SRR configuration register 120 (see FIG. 1), such as during system initialization. SRR configuration information is one type of status information. The SRR configuration register 120 may comprise an addressable location in the status information address space, as depicted in FIG. 2, or may alternatively comprise unused bits in the mode register 110 or extended mode register 112. As another alternative, one or more pins of the SDRAM device 100 may be tied to power or ground during system design, to configure the data bus subset for each SDRAM device 100 to use during SRR operations.
FIG. 3 depicts a functional block diagram of a 2-rank, ×16 SDRAM device system topology comprising a controller 102 and two SDRAM devices 100a and 100b. SDRAM device 100a, forming memory rank 0, is connected to Chip Select line 0, and SDRAM device 100b, forming memory rank 1, is connected to Chip Select line 1. The 16-bit data bus (DQ[15:0]) is depicted in FIG. 3 as separate byte lanes DQ[7:0] and DQ[15:8], controlled by byte data strobes DQS[0] and DQS[1], respectively, for ease of explication of one or more embodiments of the present invention, as will be clear from the following discussion. Other control signals, the address bus, and the like, are connected between the controller 102 and SDRAM devices 100a and 100b in a conventional manner, and are omitted from FIG. 3 for clarity.
FIG. 4 depicts a timing diagram representing a SRR issued in the system of FIG. 3 to read status information from the DRAM devices 100a and 100b. The controller 102 issues a MRS command in cycle 1 to both ranks (CS[0] and CS[1] both asserted), with a bank select of 2′b10 and an address of 0x0. A READ command is issued to rank 0 (only CS[0] asserted) tMRS cycles later, in cycle 3, and SDRAM device 100a returns status information (such as, for example, temperature information) on the data bus DQ[15:0] after the CAS latency tCL, in cycle 6. In this cycle, the controller 102 issues a READ command to rank 1 (only CS[1] asserted), and SDRAM device 100b returns status information on the data bus DQ[15:0] after the CAS latency tCL, in cycle 8. The controller 102 may issue another command beginning in cycle 9.
According to one or more embodiments of the present invention, each DRAM device 100 is configured to drive status information, such as temperature information, only to a subset of the data bus, and only drives the data strobes associated with that subset, during an SRR operation. The DRAM device 100 tri-states the remaining data bus and its associated data strobes. This configuration allows a second DRAM device 100 to drive status information on a different subset of the data bus, using the data strobes associated with the different subset. In this manner, two or more DRAM devices 100 may simultaneously drive status information on the data bus during a SRR operation, allowing the controller 102 to simultaneously read status information from two or more DRAM devices 100 at a time. This technique reduces the bus bandwidth dedicated to the SRR operation, freeing the available bandwidth for pending read, write, and refresh operations to the DRAM array.
In one or more embodiments, in the event the status information cannot be fully driven on the configured subset of the data bus during an SRR operation, the SDRAM device 100 automatically serializes the status information, and drives it on the configured to subset of the data bus in successive bus cycles. This feature takes advantage of the burst capability of the SDRAM device 100 when the width of the status information exceeds the configured data bus subset for one or more SDRAM devices 100. In one embodiment, the serialized status information is successively driven on the configured data bus subset according to the burst parameters configured in the mode register 110 and/or extended mode register 112, pertaining to burst READ operations directed to data stored in the DRAM array 104.
FIG. 5 depicts a timing diagram of a concurrent SRR operation in the memory system of FIG. 3, wherein the rank 0 SDRAM device 100a has been configured to utilize its lower byte lane DQ[7:0], and the rank 1 SDRAM device 100b has been configured to utilize its upper byte lane DQ[15:8] during SRR operations. The controller 102 issues a MRS command in cycle 1 to both ranks (CS[0] and CS[1] both asserted), with a bank select of 2′b10 and an address of 0x0 (the bank select and address buses are not depicted in FIG. 5). A READ command is simultaneously issued to both ranks (CS[0] and CS[1] both asserted) tMRS cycles later, in cycle 3. After the CAS latency tCL, in cycle 6, the rank 0 SDRAM device 100a returns the first byte of status information (such as temperature information) on the data bus bits DQ[7:0] and drives DQS[0], and in cycle 7 drives DQ[7:0] with the second byte of status information (with subsequent serial burst transfers as necessary, depending on the size of the status information to be transferred and the SDRAM device 100a burst configuration parameters). Simultaneously (with possible variations in tAC, the access timing of DQs from CLK, which is a characteristic of each individual SDRAM component), the rank 1 SDRAM device 100b returns the first byte of status information on the data bus bits DQ[15:8] and drives DQS[1] in cycle 6, and in cycle 7 drives DQ[15:8] with the second byte of status information. The controller 102 may issue another command beginning in cycle 7.
Comparing the timing diagram of FIG. 5 to that of FIG. 4 reveals that, for a CAS latency tCL=2 cycles in a 2-rank memory subsystem, the conventional SRR operation depicted in FIG. 4 requires a total of eight cycles from the initial MRS command to receiving all status information from both ranks. In contrast, the concurrent SRR operation depicted in FIG. 5 requires a total of only six cycles from the initial MRS command to receiving all status information from both ranks. The concurrent SRR operation according to this embodiment results in a 25% reduction in SRR overhead—or bus bandwidth consumed—as compared to the conventional SRR operation. A similar analysis, considering a CAS latency tCL=3 cycles, yields a 22% reduction in the overhead of concurrent SRR operation as compared with conventional SRR operation.
These embodiments of the invention are scalable to wider bus widths. FIG. 6 depicts a functional block diagram of a 2-rank, ×32 SDRAM device system topology comprising a controller 102 and four SDRAM devices 100a, 100b, 100c, and 100d. SDRAM devices 100a and 100b, forming memory rank 0, are both connected to CS[0], and SDRAM devices 100c and 100d, forming memory rank 1, are both connected to CS[1]. All SDRAM devices 100 in a given rank (i.e., 100a/100b or 100c/100d) are configured to output status information on the same subset of the data bus during a SRR operation. Conversely, parallel SDRAM devices 100 in different ranks (i.e., 100a/100c or 100b/100d) are configured to output status information on different subsets of the data bus during a SRR operation.
The 32-bit data bus (DQ[31:0]) and four data strobes (DQS[3:0]) are depicted as separate byte lanes in FIG. 6, with a notation indicating which SDRAM device 100a, 100b, 100c, 100d will drive its status information on the byte lane during SRR operations. Other control signals, the address bus, and the like, are connected between the controller 102 and SDRAM devices 100a, 100b, 100c, 100d in a conventional manner, and are omitted from FIG. 6 for clarity.
FIG. 7 depicts a timing diagram of a concurrent SRR operation in the memory system of FIG. 6, wherein the rank 0 SDRAM devices 100a and 100b have been configured to utilize the lower byte lane DQ[7:0] and DQS[0] of each SDRAM component, and the rank 1 SDRAM devices 100c and 100d have been configured to utilize their upper byte lane DQ[15:8] and DQS[1] of each SDRAM component during SRR operations. Each SDRAM 100a, 100b, 100c, 100d tri-states the non-configured portion of its data bus during SRR operations. The timing for the SRR command signaling is the same as that depicted in FIG. 5.
In this embodiment, each SDRAM device 100a, 100b, 100c, 100d is a Double Data Rate (DDR) SDRAM, and transfers four bytes of status information in burst form. As depicted in FIGS. 6 and 7, the controller 102, utilizing the full 32-bit bus DQ[31:0], receives status information from SDRAM device 100a (rank 0) on byte lane [7:0]; from SDRAM device 100c (rank 1) on byte lane [15:8], from SDRAM device 100b (rank 0) on byte lane [23:16], and from SDRAM device 100d (rank 1) on byte lane [31:24]. In this manner, two bytes of status information are received from each SDRAM device 100a, 100b, 100c, 100d in each cycle. As FIG. 7 depicts, using the concurrent SRR operation, four bytes of status information are read from each DRAM device 100a, 100b, 100c, 100d in seven cycles. Using a conventional SRR operation to read status information from each DRAM device 100a, 100b, 100c, 100d in turn would require 15 cycles. Accordingly, in this example, the concurrent SRR operation represents over a 50% decrease in SRR overhead.
The present invention is also scalable to greater than 2-rank systems, such as by issuing pairs of concurrent SRR commands. Alternatively, each SDRAM device 100 may be configured to use a smaller subset of its data bus (e.g., a nibble), and serialize the status information output as required. In this embodiment, one of two SDRAM devices 100 configured to use the same data bus byte lane may be configured to control the associated data bus strobe, with the other SDRAM device 100 configured to tri-state all data bus strobes. Such design decisions are well within the capability of those skilled in the art, and many other configurations and applications will be readily apparent to those of skill in the art, given the teaching of this disclosure.
In general, for any parallel memory devices sharing an N-bit data bus, according to one or more embodiments of the present invention, each memory device may be configured to drive status information on a different subset M of the N bits and tri-state the remaining N-M bits. Additionally, each device may be configured to drive zero, one, or more data bus strobes associated with the subset M of the N-bit data bus. In the embodiments depicted in FIGS. 3 and 6, N=16 and M=8. Other values of N and M are within the scope of the present invention.
Although described herein with reference to SDRAM memory devices 100, the present invention is not limited to SDRAM, and may be advantageously applied to read status information from any memory device. Similarly, while the status information has been described herein as temperature information related to the DRAM array 104, used to control a refresh rate, the present invention is not limited to temperature information or refresh rate control. As used herein, status information refers to any data read from a memory device other than data stored in the memory array, and may for example include a device ID 114, the contents of the mode register 110 or extended mode register 112, the contents of a SRR configuration register 120, or any other data not stored in the memory array 104. Note that a Status Register Read (SRR) command or operation may not necessarily read an actual register.
Although the present invention has been described herein with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications, and other embodiments are possible within the broad scope of the present invention, and accordingly, all variations, modifications and embodiments are to be regarded as being within the scope of the invention. The present embodiments are therefore to be construed in all aspects as illustrative and not restrictive and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.
Patent Application
20080089138
