The invention relates to a display device, and more particularly to a conducting line terminal structure for a display device to electrically connect external driving devices and internal pixel elements.
Liquid crystal displays (LCD) are the most popular flat panel display, having characteristics of low power consumption, thin profile, light weight and requiring low driving voltage. Generally, the LCD device has an array of pixel areas defined by scanning lines and data lines, each pixel area having a pixel electrode and a thin film transistor (TFT) serving as a switching device. In addition, a plurality of bonding pad structures is fabricated on the terminals of the scanning lines and the data lines respectively for electrical connection to external driving ICs by TAB (tape automatic bonding) or FPCB (flexible print circuit board), thus driving the pixel electrodes and providing image signals.
Normally, each conductive layer 24 is formed by deposition and patterning of a conductive material such as an indium tin oxide (ITO) and each conductive layer 24 also overlies a portion of the adjacent planarization layer 22. Patterning of the conductive material of the conductive layer 24 can be achieved by conventional photolithography and etching technology.
Due to overlapping of the conductive layer 24 over the planarization layer 22, the conductive lines 20 will not be exposed and potential shorting caused by particle contamination, for example, can be thus prevented.
Nevertheless, during formation of the conductive layers 24, undesired conductive residue 24a of the same conductive material of the conducive layer 24 can sometimes remain on the substrate 12 (e.g., along the edge or step height of the planarization layer 22) due to insufficient exposure during patterning of the conductive material in a boundary between the bonding area and the display area, thus electrically connecting two adjacent bonding pads 26 and causing pin-to-pin shorts of the underlying conductive lines 20.
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Hence, there is a need for improved conducting line terminal structure for a display device to prevent conductive residue remaining on the substrate, thereby reducing shorts between adjacent conducting line terminal structures.
The present invention overcomes the shorting problem in the prior art by avoiding overlap of metallization over the planarization layer during formation of the bonding pads. An insulating layer is provided to separate metallization from the step height formed by the planarization layer. The insulating layer extends below the planarization layer to the metallization layer (e.g., conductive lines on which the bonding pads are formed), but not in between adjacent metallized structures. During the metallization process for forming the conductive lines and/or bonding pads, the metal layer extends to overlap the insulating layer, but not the planarization layer or step height. Consequently, this significantly reduces the possibility of shorting of adjacent conducting lines along the edge (step height) of the planarization layer. A conductive layer may be provided below the insulating layer, which may be part of the conductive line or other conductive structures, or structurally coupled to conductive lines and/or other conductive structures overlapping the insulating layer, through via provided in the insulating layer.
Accordingly, in an embodiment of the invention, a conducting line terminal structure for a display device is provided. The conducting line terminal comprises a conducting member and an insulating layer covering a first section of the conductive member. A planarization layer is formed above a second section of the conductive member and overlaps a first section of the insulating layer and a conducting layer conductively couples to a third section of the conductive member.
An embodiment of the invention also provides a method of forming the conducting line terminal structure. In the method, an array of adjacent conducting members is formed. An insulating layer is formed to cover a first section of each conductive member. A planarization layer is formed above a second section of the array of conductive members and overlaps a first section of the insulating layer, the planarization layer spanning between adjacent conductive members. A conducting layer conductively is formed to couple third section of each conductive member and away from the second section overlapped by the planarization layer.
An embodiment of the invention also provides a display device. The display device comprises a display panel and a controller coupled to and driving the display panel to render an image in accordance with an input. The display panel comprises an array substrate with a conducting member and an insulating layer covering a first section of the conductive member. A planarization layer is formed above a second section of the conductive member and overlaps a first section of the insulating layer and a conducting layer conductively couples to a third section of the conductive member.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
a˜6d are cross sections along line 5-5 of
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Herein, each conducting line 110 has a structure comprising three independent conductive members 104, 106 and 108. Conductive member 104 underlies conductive members 106 and 108 and electrically connects thereto through the contact holes 112 and 114 formed in an insulating layer 116, respectively. The insulating layer 116 overlies the conductive member 106 and between the conductive members 104 and 108, providing insulation thereof. The conducting lines 110 can electrically connect external driving devices and internal pixel elements (not shown) formed in the display area.
Herein, a portion of the insulating segment 116, a portion of the underlying conductive member 104, and the conductive member 108 within the display area are covered by a planarization layer 118. The conductive member 106 formed within the bonding area, not covered by the planarization layer 118, is exposed as a terminal portion of each conducting line 110. In addition, a conductive layer 120 is formed overlying and electrically connected to the conductive member 106, thus forming a bonding pad 122.
Due to passivation of the planarization layer 118 and the insulating layer 116 to the conductive members 108 and the underlying conductive member 104 of the structure of the conducting lines 110 shown in
Fabrication of the conducting line 110 along line 6-6 in
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Next, an insulating layer 116 is formed over the array substrate 102 to cover the array substrate 102 and the conductive member 104. The insulating layer 116 can be, for example, an oxide layer. In the insulating layer 116, contact holes 112 and 114 are then respectively formed in relative position above both ends of the conductive member 104 by patterning the insulating layer 116.
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Next, a planarization layer 118 is formed over the array substrate 102 and patterned to cover the conductive member 108 within the display area and a portion of the adjacent insulating layer 116, exposing the conductive member 106 in the bonding area.
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Herein, as shown in
In alternate embodiments (not shown), the conductive member 104 may be extended to form, or may be part of, the conductive member 108 and/or conductive member 106. In fact, a single, unitary conductive member (e.g., in the form of a conductive line) may comprise members 104, 106 and 108. Further, it is not necessary to have conductive members 106 and 108 be formed in the same layering process. Also, it is not necessarily to have the insulating layer 116 under the conductive member 106 and/or conductive member 108. There may be one or more intermediate layers between the planarization layer and the conductive member 108. These and other variations are well within the scope and spirit of the present invention.
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Moreover, the display panel 100 shown in
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.