The present invention relates to a semiconductor device and, more particularly, to a non-volatile memory device having a structure where a conductive organic material layer is disposed between upper and lower electrodes and a method for fabricating the same.
A volatile dynamic random access memory (DRAM) device and a non-volatile flash memory device represent two types of memory devices. In the DRAM device, a length of a channel underneath a gate of a cell transistor is adjusted according to a voltage supplied to the gate and a cell capacitor is charged or discharged by electrons moving through the channel formed between source and drain terminals of the cell transistor, so that cell data is read by detecting the charged or discharged state of the cell capacitor. Since the DRAM device is a volatile memory device, when power is not supplied to the device, the cell data stored in the device may be lost due to a leakage current. Thus, the cell capacitor should be continuously charged to maintain the cell data, which increases power consumption.
On the other hand, in a non-volatile flash memory device such as a NAND type flash memory device, Fowler-Nordheim (FN) tunneling is generated due to a voltage supplied to a control gate and a channel region. Then, by FN tunneling, a floating gate is charged with electrons or the electrons are discharged from the floating gate. A threshold voltage of the channel region changes according to the charged or discharged state of the floating gate and the flash memory device distinguishes 0 or 1 data by detecting a change of the threshold voltage. Since the flash memory device uses FN tunneling, the voltage used in the device becomes very high. Furthermore, since a data read/write operation is performed by charging/discharging the electrons in/from the floating gate formed with polysilicon through FN tunneling, a data processing speed becomes slow, i.e., μ-second level.
To fabricate the typical memory device, since at least several tens of processes need to be performed and a memory cell size is relatively great (e.g., 8 F2), it is difficult to highly integrate the device, reduce product cost, and maintain a high yield.
Accordingly, research institutes and enterprises conduct various studies to develop next generation memory devices that overcome limitations of the DRAM and the flash memory devices while keeping their advantages.
Research for the next generation memory devices are being conducted in various fields according to materials used in a unit cell of the devices. For instance, one of the devices applies current into a phase transfer material and detects 0 or 1 data by using resistance difference obtained according to whether the material is cooled to a solid state having less resistance or an amorphous state having greater resistance. Another one of the devices uses the bistable conductive characteristics having high resistance and low resistance in the same voltage when applying a voltage to a conductive organic material. Still another one of the devices uses ferroelectrics. Further still another one of the devices uses a ferromagnetic material having N and S poles to store data. Furthermore, there is study being conducted for a non-volatile memory device employing a planar floating gate using nanocrystals of metal, silicon or compound semiconductor instead of silicon of a flat structure.
However, study groups researching the next generation memory devices have a common problem of finding the optimized process conditions for applying the above materials to the highly integrated memory devices.
Particularly, a non-volatile memory device using a conductive organic material, e.g., a polymer (Po) RAM device, has not been applied to an actual fabrication process and it is not easy to find the precise fabrication conditions. That is, since it is difficult to repetitively form nanocrystals with regular size and distribution in the conductive organic material, a threshold voltage and a bistable conductive characteristic, i.e. Ion/Ioff, become irregular.
Embodiments of the present invention relate to a non-volatile memory device, a method of operating the memory device, and a method for fabricating the memory device.
In accordance with the embodiments of the present invention, there are provided various memory devices including nanocrystals capable of stabilizing a threshold voltage and an Ion/Ioff rate and methods for forming the nanocrystals, so that data may be not damaged even though power is not supplied and the device is highly integrated while having a memory cell size of 4F2. Furthermore, the present invention provides devices and methods capable of keeping a high processing speed of a PoRAM device and securing a stable size and distribution of the nanocrystals. In addition, in accordance with the present invention, a unit cell can have a multi-level data using an intermediate resistance state of a bistable conductive characteristic and the non-volatile memory device with a stack structure of unit cells and the method for fabricating the same are provided.
In accordance with an aspect of the present invention, there is provided a non-volatile memory device including lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.
In accordance with another aspect of the present invention relates to a method for operating a non-volatile memory device having a plurality of unit cells. Each unit cell has first and second electrodes, a conductive organic material layer provided between the first and second electrodes, and a nanocrystal layer provided within the conductive organic material layer. The nanocrystal layer includes a plurality of nanocrystals. Each nanocrystal is surrounded by an amorphous barrier. The method includes applying no more than a first voltage difference between the first and second electrodes of the device to place the unit cell in a first resistance state; applying no more than a second voltage difference between the first and second electrodes to place the unit cell in a second resistance state that is of a lower resistance state than the first resistance state, the second voltage difference being greater than the first voltage difference; and applying no more than a third voltage difference between the first and second electrodes to place the unit cell in a third resistance state that is of a lower resistance state than the first resistance state and a higher resistance state than the second resistance state, the third voltage difference being greater than the second voltage difference.
In accordance with still another aspect of the present invention, there is provided a non-volatile memory device including lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein a read operation is performed when an input voltage coupled to the lower and the upper electrodes is in a first voltage range, a first write operation is performed for writing a first input data when the input voltage is in a second voltage range higher than the first voltage range, a second write operation is performed for writing a second input data when the input voltage is in a third voltage range higher than the second voltage range, and an erase operation is performed for erasing the first or the second input data when the input voltage is in a fourth voltage range higher than the third voltage range.
In accordance with further still another aspect of the present invention, there is provided a non-volatile memory device including a first cell and a second cell, wherein the first and the second cells are vertically stacked, wherein the first cell includes first and second electrodes over a substrate, a first conductive organic material layer between the first and the second electrodes, and a first nanocrystal layer located within the first conductive organic material layer, and the second cell includes the second and third electrodes over the substrate, a second conductive organic material layer between the second and the third electrodes, and a second nanocrystal layer located within the second conductive organic material layer, wherein each of the first and the second nanocrystal layers has a plurality of nanocrystals surrounded by an amorphous barrier.
In accordance with further still another aspect of the present invention, there is provided a non-volatile memory device including lower and upper electrodes over a substrate and a polymer layer located between the lower and the upper electrodes, wherein the polymer layer includes a plurality of nanocrystals surrounded by an amorphous barrier, which are dispersed in the polymer layer.
In accordance with further still another aspect of the present invention, there is provided a non-volatile memory device including a first cell and a second cell, wherein the first and the second cells are vertically stacked, wherein the first cell includes first and second electrodes over a substrate and a first polymer layer between the first and the second electrodes, and the second cell includes the second and third electrodes over the substrate and a second polymer between the second and the third electrodes, wherein each of the first and the second polymer layers has a plurality of nanocrystals surrounded by an amorphous barrier material, which are dispersed in the polymer layer.
In accordance with further still another aspect of the present invention, there is provided a method for fabricating a non-volatile memory device, the method including providing a substrate, forming a lower electrode over the substrate, forming a first conductive organic material layer over the lower electrode, forming a nanocrystal layer over the first conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, forming a second conductive organic material layer over the nancrystal layer, and forming an upper electrode over the second conductive organic material layer, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.
In accordance with further still another aspect of the present invention, there is provided a method for fabricating a non-volatile memory device, the method including providing a substrate, forming a lower electrode over the substrate, forming a first conductive organic material layer over the lower electrode, forming a first barrier material layer over the first conductive organic material layer, forming a certain metal layer over the first barrier material layer, forming a second barrier material layer over the certain metal layer, forming a second conductive organic material layer over the second barrier material layer to thereby provide a first resultant structure, curing the first resultant structure to thereby provide a second resultant structure, and forming an upper electrode over the second conductive organic material layer of the second resultant structure, wherein, during the curing of the first resultant structure, a nanocrystal layer having a plurality of nanocrystals surrounded by an amorphous barrier is formed between the first and the second conductive organic material layers, the nanocrystals formed with the certain metal and the amorphous barrier formed with the first and the second barrier materials.
In accordance with further still another aspect of the present invention, there is provided a method for fabricating a non-volatile memory device, the method including providing a substrate, forming a lower electrode over the substrate to thereby provide a resultant structure, forming a polymer layer where a plurality of nanocrystals are dispersed, wherein each of the nanocrystals is surrounded by a corresponding amorphous barrier, and forming an upper electrode over the polymer layer.
In accordance with further still another aspect of the present invention, there is provided a method for fabricating nanocrystals, including providing a substrate, forming a first barrier material layer over the substrate, forming a metal layer over the first barrier material layer, forming a second barrier material layer over the metal layer to provide a resultant structure, and curing the resultant structure to form the nanocrystals covered with the first and the second barrier materials.
Specified embodiments of the present invention relate to a non-volatile memory device, a method of operating the device, and a method for fabricating the device.
Hereinafter, non-volatile memory devices, e.g., PoRAM devices, are separately described according to type of conductive organic material used. That is, the non-volatile memory devices will be separately described in two cases, i.e., the conductive organic material being a low molecular compound (or low molecular material), e.g., AIDCN, Alq3, and α-NPD, and the conductive organic material being a high molecular compound (or high molecular material), e.g., PVK. This is because it is desirable to apply different methods to fabricating the non-volatile memory devices according to the type of conductive organic material and the non-volatile memory devices have different structures according to the applied fabrication methods.
A method for fabricating the non-volatile memory device using the low molecular compound as the conductive organic material is described with reference to
Referring to
The substrate 11 may be an insulation substrate, a semiconductor substrate, or a conductive substrate. That is, the substrate 11 may be one of a plastic substrate, a glass substrate, an aluminum oxide (Al2O3) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a lithium aluminum oxide (LiAl2O3) substrate, a boron nitride (BN) substrate, an aluminum nitride (AlN) substrate, a silicon-on-insulator (SOI) substrate, and a gallium nitride (GaN) substrate. When the semiconductor substrate or the conductive substrate is used, the lower electrode 12 and the substrate 11 may be separated by an insulation layer.
The lower and the upper electrodes 12 and 17 may include various types of conductive materials according to one embodiment. The lower and the upper electrodes 12 and 17 may also include metal having low electrical resistance and a good interfacial characteristic for the conductive organic material. For example, the lower and the upper electrodes 12 and 17 may include one selected from a group consisting of aluminum (Al), titanium (Ti), zinc (Zn), iron (Fe), nickel (Ni), stannum (Sn), plumbum (Pb), copper (Cu), and a combination thereof.
The first and the second organic material layers 13 and 16 are made of low molecular compounds and may include one of 5-imidazoledicarbonitrile (AIDCN), α-N-diphenyl bendizine (α-NPD) and tris (8-hydroxyquinoline) aluminum (Alq3). The AIDCN is expressed as the following formula.
The α-NPD is expressed as the following formula.
The Alq3 is expressed as the following formula.
As described above, the nanocrystal layer 15 includes the plurality of nanocrystals 15A and the amorphous barrier 15B surrounding the nanocrystals 15A. The nanocrystal layer 15 may be formed by depositing a first metal layer which can be oxidized and then performing a plasma oxidation process on the first metal layer. This is for forming nanocrystals 15A with a constant size and distribution to thereby secure a stable device performance and form the amorphous barrier 15B through a simple process. Accordingly, the nanocrystals 15A are made of the first metal and the amorphous barrier 15B includes the first metal oxide material. For instance, when the nanocrystals 15A include Al, the amorphous barrier 15B may include AlxOy, particularly Al2O3, where x and y are positive integers. When the nanocrystals 15A include Ni, the amorphous barrier 15B may include NixOy, particularly NiO. However, the nanocrystals 15A may also include other metals that can be oxidized. For instance, the nanocrystals 15A may include one of Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and an alloy thereof. The amorphous barrier 15B may include an oxide material of the above-selected metal. The method for fabricating the nanocrystal layer 15 will be described in detail with reference to
The nanocrystal layer 15 may be formed to have a thickness of approximately 1 nm to approximately 40 nm. In one embodiment, the nanocrystal layer 15 is approximately 10 nm to approximately 15 nm. In this embodiment, the nanocrystal layer 15 has a single layer. However, the nanocrystal layer 15 may include a stack structure having multiple layers. Such a stack structure may have from 2 to 8 layers and, more desirably, from 2 to 4 layers. When forming the nanocrystal layer 15 with the stack structure, it is possible to secure improved data retention and maintain an effective energy gap. In one embodiment, the layers of the stack structure of the nanocrystal layer 15 are of substantially the same thickness.
When a unit cell is formed to include the nanocrystal layer 15 with the nanocrystals 15A and the amorphous barrier 15B surrounding the nanocrystals 15A between the first and the second conductive organic material layers 13 and 16, the device can have various resistance states and thus output various levels of current according to voltage levels of voltages coupled to the lower and the upper electrodes 12 and 17, so that more than one bit data can be stored in the unit cell. The above device operation will be described with reference to
Referring to
As described, two cells are stacked and thus it is possible to highly integrate the device within a certain area. More than three cells can be stacked by repeatedly performing the same process as shown above. Furthermore, even though more than two cells are stacked, each of the cells can have various resistance states and output multi levels of current. Operational characteristics thereof will be described with reference to
Referring to
In detail, the substrate 211 is loaded in a chamber (not shown) for metal deposition. A region of the substrate 211 where the first electrode 212 is to be formed is exposed using a first shadow mask (not shown). Then metal is evaporated with a chamber pressure of approximately 10−6 Pa to approximately 10−3 Pa, a deposition rate of approximately 2 Å/s to approximately 7 Å/s and a temperature of approximately 1,000° C. to approximately 1,500° C., so that a metal layer is formed on the exposed region of the substrate 211. This metal layer becomes the first electrode 212. A cleaning process may be performed before and/or after depositing the metal layer for the first electrode 212.
The first electrode 212 is made of Al in the present embodiment. However, the first electrode 212 may also include one selected from a group consisting of Ti, Zn, Fe, Ni, Sn, Pb, Cu and an alloy thereof. The first electrode 212 is formed to have a thickness of approximately 50 nm to approximately 100 nm.
It is effective to use a silicon (Si) substrate or a glass substrate as the substrate 211. When the substrate 211 is the Si substrate, an insulation layer should be deposited thereon. The insulation layer may be an oxide- or a nitride-based material layer.
Referring to
The first conductive organic material 213 may be made of one of the AIDCN, the α-NPD, and the Alq3. The first conductive organic material layer 213 is formed to have a thickness of approximately 10 nm to approximately 100 nm.
Referring to
In detail, the substrate 211 with the first conductive organic material layer 213 is loaded in a chamber (not shown) for depositing metal. A portion of the first conductive organic material layer 213 where the nanocrystal layer 215 is to be formed is exposed using a third shadow mask (not shown). At this time, the portion of the first conductive organic material layer 213 is exposed to make the nanocrystal layer 215 overlap with a portion of the first electrode 212 below the first conductive organic material layer 213. Thus, the nanocrystal layer 215 partially overlaps with the first electrode 212. The region exposed by the third shadow mask has substantially the same shape as that of the first conductive organic material layer 213, e.g., a square shape.
The metal layer 214 is formed to have a thickness of approximately 1 nm to approximately 40 nm on the exposed portion of the first conductive organic material layer 213 by performing the evaporation process with a chamber pressure of approximately 10−6 Pa to 10−3 Pa, a deposition rate of approximately 0.1 Å/s to approximately 7.0 Å/s, and a temperature of approximately 800° C. to approximately 1,500° C. When the metal layer 214 is made of Al, the deposition rate ranges from approximately 1.0 Å/s to approximately 5.0 Å/s. When the metal layer 214 is made of Ni, the deposition rate ranges approximately 0.1 Å/s to approximately 1.0 Å/s. Since the metal layer 214 has a high deposition rate, it is formed as a metal film with a grain boundary (refer to
The substrate 211 having the metal layer 214 is loaded in a plasma oxidation chamber. The plasma oxidation process is performed by injecting an O2 gas with an RF power of approximately 50 W to approximately 300 W, an AC bias of approximately 100 V to approximately 200 V, and a pressure of approximately 0.5 Pa to approximately 3.0 Pa. The plasma oxidation process may be performed for approximately 50 seconds to approximately 500 seconds. The O2 plasma is implanted along a boundary of the metal layer 214 with the grain boundary, so that the metal layer 214 is oxidized along its boundary. As a result, a plurality of nanocrystals 215A and an amorphous metal oxide material, i.e., the amorphous barrier 215B surrounding the nanocrystals 215A, are formed (refer to
The deposition and the plasma oxidation processes may be performed a plurality of times on the metal layer 214 to form the nanocrystal layer 215 having a stack structure with a plurality of nanocrystal films. The nanocrystal films constituting the nanocrystal layer 215 may have the same thickness or different thicknesses according to thicknesses of deposited metal layers therefore. In one embodiment, each of the nanocrystal films has substantially the same thickness.
Referring to
In detail, the substrate 211 having the nanocrystal layer 215 is loaded in a chamber (not shown) for depositing the conductive organic material to form the second conductive organic material layer 216. The first conductive organic material layer 213 on which the nanocrystal layer 215 is formed is exposed using the second shadow mask. The second conductive organic material layer 216 is formed over the exposed portions of the nanocrystal layer 215 and the first conductive organic material layer 213 by performing an evaporation process. The evaporation process is performed with a chamber pressure of approximately 10−6 Pa to approximately 10−3 Pa, a deposition rate of approximately 0.2 Å/s to approximately 1.5 Å/s and a temperature of approximately 150° C. to approximately 400° C.
In the present embodiment, the second conductive organic material layer 216 is made of the same material as that for the first conductive organic material layer 213 and it is formed to have a thickness of approximately 10 nm to approximately 100 nm. The second conductive organic material layer 216 may be of a different material in another embodiment. Since the nanocrystal layer 215 is formed over a portion of the first conductive organic material layer 213 and then, the second conductive organic material layer 216 is deposited thereon, the second conductive organic material layer 216 is formed to cover the nanocrystal layer 215. The second conductive organic material layer 216 may have the same thickness as that of the first conductive organic material layer 213, or be thinner or thicker.
Referring to
The second electrode 217 is made of Al. However, the second electrode 217 may be made of one selected from a group consisting of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and a combination thereof. The second electrode 217 may be formed to have a thickness of approximately 60 nm to approximately 100 nm.
Although it is not shown, a separate metal line forming process can be performed to respectively connect the first and the second electrodes 212 and 217 to external electrodes. The first and the second electrodes 212 and 217, the first and the second conductive organic material layers 213 and 216, and the nanocrystal layer 215 may be formed in-situ in a vacuum atmosphere. That is, the chambers for forming the first and the second electrodes 212 and 217, the first and the second conductive organic material layers 213 and 216, and the nanocrystal layer 215 can be disposed in a singular deposition system. For instance, the deposition processes are performed in a singular system where the chamber for depositing metal, the chamber for depositing the conductive organic material, the plasma generation chamber for the plasma oxidation, a cooling chamber, a load lock chamber, and a shadow mask chamber are connected to one transfer module. Thus, when the substrate in the chamber for depositing metal is transferred to the chamber for depositing the conductive organic material, the substrate is not exposed onto the atmosphere and can move in the transfer module in the vacuum atmosphere. Of course, each of the chambers may be connected to different systems.
In accordance with the above embodiment, the metal layer, the conductive organic material layer, and the nanocrystal layer are formed by performing the evaporation processes using the shadow mask without performing an etch process. However, other methods can be applied to form the non-volatile memory devices. The metal layer, the conductive organic material layer, and the nanocrystal layer can be formed by performing a thermal evaporation process, an E-beam deposition process, a sputtering process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Particularly, the metal layer and the conductive organic material layer are formed over a whole surface of the substrate and then, a patterning process is performed thereon. That is, after depositing the metal or the conductive organic material over the whole surface of the substrate, an etch process using a mask is performed to remove the deposited metal or conductive organic material on a region where the metal layer or the conductive organic material layer is not formed. For the oxidation, a wet or a dry oxidation process may be performed.
Referring to
Referring to
Referring to
Hereinafter, experimental examples for forming the Al nanocrystal layer and the Ni nanocrystal layer are described to show characteristics of the nanocrystal layer formed by the deposition of the metal layer and the plasma oxidation processes.
Referring to
Referring to
Referring to
This result indicates that the O2 plasma is implanted along the boundary of the metal layer from on the lower conductive organic material layer during the plasma oxidation process for forming the Al nanocrystal layer and then, the lower border of the metal layer interfacing with the lower conductive organic material layer is also sufficiently oxidized. As a result, the Al nanocrystals are separated by the amorphous Al2O3, thereby being properly isolated.
Referring to
Referring to
Referring to
That is, it is noted that when the Ni metal layer is deposited and the O2 plasma oxidation process is performed thereon, the Ni nanocrystals and the amorphous Ni oxide material surrounding the Ni nanocrystals are formed.
Hereinafter, the non-volatile memory device with a stack structure of the first conductive organic material layer/the nanocrystal layer/the second conductive organic material layer between the lower and the upper electrodes is described. Particularly, the experiment was carried out in forming the Al nanocrystal layer and the Ni nanocrystal layer by employing the method illustrated in
Referring to
For instance, when connecting the lower electrode 12 to the ground and the upper electrode 17 to a certain voltage source to sequentially increase the voltage of the voltage source in a positive direction, the unit cell has a high resistance state Ioff. In the high resistance state, the current increases slowly until a threshold voltage Vth is reached. Then, when the voltage difference between the electrodes 12 and 17 is greater than a certain level, i.e., a critical voltage or a threshold voltage Vth, the unit cell is transformed to have a low resistance state Ion where the current increases rapidly. The current output by the unit cell increases as the voltage applied to the upper electrode increases to a peak current voltage Vp. Beyond the peak current voltage Vp, the unit cell is transformed to have a negative differential resistance (NDR) state where the current decreases as the voltage increases. The unit cell is in the NDR state until the voltage applied to the upper electrode reaches a reset voltage Ve (or erase voltage). The unit cell again outputs a current increasing as the voltage applied to the upper electrode increases. That is, the unit cell has various current and resistance states according to the potential difference between the upper and lower electrodes. Here, the peak current voltage Vp indicates a voltage at the point where the current of the unit cell reaches the peak or where a negative current is generated.
The non-volatile memory device having various current or resistance states performs a data read operation in a first voltage range, a data write operation in a second voltage range, an intermediate data write operation in a third voltage range, and an erase operation in a fourth voltage range. The second voltage range is higher than the first voltage range. The third voltage range is higher than the second voltage range. The fourth voltage range is higher than the third voltage range. The first voltage range has a voltage not more than the threshold voltage Vth, the second voltage range has a voltage more than the threshold Vth and not more than the peak current voltage Vp, the third voltage range has a voltage more than the peak current voltage Vp and not more than a certain voltage Ve, and the fourth voltage range has a voltage more than a certain voltage Ve. Hereinafter, this mechanism is described in detail.
To place the non-volatile memory device in the low resistance state Ion, a voltage more than the threshold voltage Vth, i.e., a first program voltage, is supplied to the memory device. That is, as illustrated in
To place the memory device in the NDR state, a voltage more than the peak current voltage V, and not more than a reset voltage Ve, i.e., the second program voltage, is supplied to the memory device. That is, as illustrated in
When supplying the certain voltage Ve after the NDR state range, the resistance state of the device is changed to the high resistance state. That is, the device is reset.
As a result, it is possible that the first program voltage in the low resistance state Ion is supplied to store a value corresponding to a first data in the device and the second program voltage in the NDR state is supplied to store a value corresponding to a second data in the device.
Particularly, since the level of the output current changes according to the voltage level supplied in the NDR range, various values corresponding to the second data can be stored in the device. For instance, as shown in
As a result, the unit cell is embodied as a multi-level cell with at least three levels.
Hereinafter, the unit cell is described as having various current or resistance states.
When carriers are not charged in the nanocrystals due to a gap of energy levels between the nanocrystal layer (including the nanocrystals and the amorphous barrier surrounding the nanocrystals) and the conductive organic material layer, the flowing current delicately increases at a certain voltage. However, when the voltage coupled to both of the conductive organic material layers is more than a certain critical voltage, e.g., the threshold voltage Vth, the carriers are charged in the nanocrystals and thus the flowing current rapidly increases. When the carriers are charged in the nanocrystals, the flowing current increases tens of times to tens of thousands times compared to the case when the carriers are not charged. Furthermore, when the voltage coupled to both of the conductive organic material layers is in the NDR range, the carriers are partially charged or partially discharged, so that the flowing current has an intermediate current lower than that in the case of the carriers being completely charged and higher than that in the case of the carriers not being charged. When the voltage higher than that in the NDR range, e.g. the reset voltage Ve, is coupled to both of the conductive organic material layers, the carriers charged in the nanocrystals are completely discharged.
Meanwhile, as shown in
As described above, in accordance with an embodiment of the present invention, the non-volatile memory device may have a double cell structure of two unit cells sequentially stacked (refer to
Referring to
Hereinafter, retention and endurance of the non-volatile memory device are described.
Referring to
Referring to
Referring to
Referring to
Referring to
In the drawings, the lower graphs in
The non-volatile memory device including actual circuits operates in response to a pulse signal coupled thereto.
Referring to
Referring to
In
However, it is possible to use a high molecular compound so as to form a conductive material layer and other processes than the deposition of the metal layer and the plasma oxidation process can be employed to form the nanocrystal layer. Hereinafter, the other processes are described with reference to
The detailed description of the processes already described referring to
Referring to
Referring to
Referring to
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Referring to
Referring to
Referring to
Referring to
Different from the method described in
Referring to
The energy bands shown in
Unlike the aforementioned embodiments, formation of the polymer layer and the nanocrystals surrounded by the barrier material is simultaneously performed in this embodiment. Therefore, in accordance with this embodiment, the nanocrystals and the barrier material surrounding the nanocrystals are separately disposed in the polymer layer.
Referring to
Referring to
Referring to
Referring to
In the process (A), metal salt, e.g., chloroauric acid (HAuCl4) is soluble in deionized (DI) water which is an aqueous solvent to make an aqueous solution of metal salt. At this time, the metal salt, i.e., HAuCl4, is ionized to H+ and AuCI4− to function as an Au source. Further, a tetraoctylammonium (TOAB) is soluble in a toluene solvent that is a non-aqueous solvent, so that a toluene solution including ionized TOAB is formed. In a subsequent process, the ionized TOAB functions as a phase transfer catalyzer for transferring the aurum tetrachloride complex ion AuCl4− containing metal to the toluene solution.
In the process (B), when stirring the aqueous solution of the metal salt and the toluene solution where the TOAB is soluble, the AuCl4− is transferred to the toluene solution. The stirring process may be performed at a rate of more than 500 rpm.
Then, carbazole terminated thiol (CB) is added as a stabilizer into the toluene solution to stabilize the dispersion of the Au nanocrystals and then stirred. This stirring process may be performed for approximately 5 minutes to approximately 20 minutes. A molecular formula of the CB which is the dispersion stabilizer is C23H31NS and a chemical name thereof is 11-carbazolyl dodecane thiol.
In the process (c), sodium brohydride (NaBH4) is added as a reducer for reducing the AuCl4− into the toluene solution where the CB is added in the process (B) and then stirred. This stirring process may be performed at a rate of more than approximately 500 rpm and at room temperature for approximately 3 hours to approximately 10 hours.
As a result, as shown in the process (D), the compound of the Au nanocrystals and the CB is formed in the toluene solution. The CB is formed to surround the Au nanocrystals, so that the CB functions as not only the dispersion stabilizer but also the electron tunneling barrier like the aforementioned barrier materials.
In the process (E), the toluene solution is evaporated, so that the compound of the Au nanocrystals and the CB remains. The evaporation may be performed in a rotary evaporator by applying a low pressure of not more than approximately −1 Bar.
In the process (F), the compound of the Au nanocrystals and the CB is soluble in a non-aqueous solution, e.g., a chloroform solution, to be mixed with the polymer. The PVK as the polymer is mixed with the chloroform solution.
Finally, in the process (G), a final solution including the Au nanocrystals surrounded by the CB and the polymer is formed. When this solution is spin coated on the substrate, a structure of the polymer layer 34 in
The energy band in
Referring to
A non-volatile memory device generally includes a cell array having a plurality of cells and a peripheral circuit performing an operation of reading data from a memory cell or writing data to the memory cell. Since the non-volatile memory device in accordance with the present invention has a structure similar to that of the general non-volatile memory device, the memory cell 2200 is located in the cell array, and the drive unit 2400 and the control unit 2600 are arranged in the peripheral circuit.
In particular, the memory cell 2200 has substantially the same structure as that described in
Furthermore, the memory cell 2200 may have the structure described in
The drive unit 2400 drives the memory cell 2200. That is, the drive unit 2400 provides an input voltage to the lower and the upper electrodes of the memory cell 220 and thus the memory cell 2200 becomes to have a high resistance state, a low resistance state and a negative resistance state according to a voltage level of the input voltage. As a result, the memory cell 2200 has a multi-level output current during a read operation.
The drive unit 2400 supplies biases for the program operation, the read operation and the erase operation described above in detail with reference to
The control unit 2600 controls the memory cell 2200 and the drive unit 2400 according to an operation mode of the device.
In accordance with the embodiments of the present invention, there are introduced various methods for forming the nanocrystals capable of stabilizing a threshold voltage and an Ion/Ioff rate of the non-volatile memory device. When the methods are applied, data may be retained even though power is not supplied and the device is highly integrated while having a memory cell size of 4F2. Furthermore, a high processing speed of the PoRAM device can be kept and a stable size and distribution of the nanocrystals are secured. In addition, in accordance with the present invention, a unit cell can have a multi-level data using an intermediate resistance state of a bistable conductive characteristic and the non-volatile memory device with a stack structure of unit cells and the method for fabricating the same are provided.
While the present invention has been described with respect to the specific embodiments, the above embodiments of the present invention are illustrative and not limitative. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Number | Date | Country | Kind |
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10-2007-0040519 | Apr 2007 | KR | national |
10-2008-0034118 | Apr 2008 | KR | national |
The present invention is a divisional of U.S. patent application Ser. No. 12/108,465, filed on Apr. 23, 2008, which claims priority of Korean patent application number 2007-0040519, filed on Apr. 25, 2007, both of which are incorporated by reference in their entirety.
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Number | Date | Country | |
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Parent | 12108465 | Apr 2008 | US |
Child | 13286861 | US |